Actions
Forum Thread Details
  • State Not Answered
  • Replies 4 replies
  • Subscribers 329 subscribers
  • Views 325 views
  • Users 0 members are here
Related

AMP Zedboard Vivado

Former Member

I am trying to run a simple application where core 0 writes to a shared register and core 1 reads from that register, printing out the value.

I created a custom IP to be the shared register in the FPGA. I've confirmed with one core that I am able to read and write to that register.

However I cannot figure out how to get both of these to run simultaneously. Looking online it seems like I might need to go the route of something like FreeRTOS.

Is there really no way for me to program this within the Xilinx SDK?

All of the examples I have found for AMP are either for Altera tools, ISE, or different boards.

Thanks

edit:
I attempted to create a bootable SD of this using:
FSBL > system.bit > core0.elf > core1.elf

When I don't use the core1.elf to generate the boot.bin the program loads and functions correctly (different functionality than described before - it just writes and reads from a register).

When I use the core1.elf in the boot.bin generation nothing works at all.

Parents
  • 0

    Hi Steve,

    The FSBL from Zynq Software SpeedWay training is the same stock FSBL.  The only thing that is special for AMP is making sure that you get the order of the executable files (and the execution memory space) listed correctly in the BOOT.BIN container file.

    As for standalone_amp BSP, there are not really many differences between the stock standalone BSP and the AMP one.  All I did was take a diff of all of the files between the standalone_amp BSP that is provided in XAPP1079 and the stock standalone BSP that comes with Xilinx SDK.  Then I copied the latest stock version of standalone BSP from the Xilinx install folder and make a copy called standalone_amp and merge the differences from the version provided with XAPP1079.  I have done this process twice already, once migrating the SpeedWay labs to 2013.3 tools and again migrating to 2014.4 tools and I didn't have any problems. 

    I am not aware of a more detailed guide than XAPP1079.

    The changes are mostly trivial where some critical processor resources are not reinitialized by the second CPU.

    Regards,

    -Kevin

Reply
  • 0

    Hi Steve,

    The FSBL from Zynq Software SpeedWay training is the same stock FSBL.  The only thing that is special for AMP is making sure that you get the order of the executable files (and the execution memory space) listed correctly in the BOOT.BIN container file.

    As for standalone_amp BSP, there are not really many differences between the stock standalone BSP and the AMP one.  All I did was take a diff of all of the files between the standalone_amp BSP that is provided in XAPP1079 and the stock standalone BSP that comes with Xilinx SDK.  Then I copied the latest stock version of standalone BSP from the Xilinx install folder and make a copy called standalone_amp and merge the differences from the version provided with XAPP1079.  I have done this process twice already, once migrating the SpeedWay labs to 2013.3 tools and again migrating to 2014.4 tools and I didn't have any problems. 

    I am not aware of a more detailed guide than XAPP1079.

    The changes are mostly trivial where some critical processor resources are not reinitialized by the second CPU.

    Regards,

    -Kevin

Children
No Data