I am trying to run a simple application where core 0 writes to a shared register and core 1 reads from that register, printing out the value.
I created a custom IP to be the shared register in the FPGA. I've confirmed with one core that I am able to read and write to that register.
However I cannot figure out how to get both of these to run simultaneously. Looking online it seems like I might need to go the route of something like FreeRTOS.
Is there really no way for me to program this within the Xilinx SDK?
All of the examples I have found for AMP are either for Altera tools, ISE, or different boards.
Thanks
edit:
I attempted to create a bootable SD of this using:
FSBL > system.bit > core0.elf > core1.elf
When I don't use the core1.elf to generate the boot.bin the program loads and functions correctly (different functionality than described before - it just writes and reads from a register).
When I use the core1.elf in the boot.bin generation nothing works at all.
