Unfortunately a 2015.3 design contains a newer version of the AXI VDMA IP core which is not compatible with the driver patch used on the older ISE 14.4 design (which used an older version of VDMA).
We are planning an update which includes an updated version of the kernel driver to support the newer VDMA IP core. I will post back to this thread when I have more information on the update.
Thank you for your response. Will wait for it. I would like to know why this design does not use Xilinx vtc? Is there any specific reason. I am trying to use Xilinx drm, but get vtc issues.
IIRC, at the time we originally developed this reference design, the VTC was part of the video processing package which was not available for free.
We knew that there were specific panels that we were targeting and, using our own timing generator, we could generate the timing for with relative simplicity (an perhaps have a more compact logic design).
We have not gone back to see how much effort would be required to migrate to the Xilinx VTC.
