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Terminal read from zedboard

deaxman

When using xillinux, I have been using hexdump -C -n 16 /dev/xillybus_mem_8 to read data that is stored to the memory in the zedboard and thus communicate values to the terminal.  This only gives me 2 hex positions at a time though and just repeats those two even though I specified 16 slots.  Is there any way to fix this and get more digits of hex?  Thanks!

  • 0

    Hi,

    Hexdump is a rich utility, which allows you to print out data in several formats, including custom defined.

    For example, to print out 32-bit words one after another, go

    hexdump -v -e '1/4 "%08x " "
    "'

    The syntax is somewhat tangled, but is nevertheless documented in hexdump's man page:

    http://unixhelp.ed.ac.uk/CGI/man-cgi?hexdump+1

    If you get the same 8-bit value over and over again, it's most likely because that is what the array contains. Or, it's possible that it isn't read correctly. For example, it could be that you didn't connect the address lines correctly to the piece of logic that reads from the array (in the PL part).

    Regards,
       Eli

  • 0

    I understand how to use hexdump I think, I haver read the page on it.  What confuses me is that this is reading from the mem_8 8bit storage so there are only 8 bits which makes sense that there are only 2 hex digits, how do I put more info through?  Right now I am replacing demoarray with my own values in the xillydemo file but demoarray is mapped to mem_8 and I would like to send a 32 bit message to the terminal.

  • 0

    If you want 32 bits per word, and/or possibly a wider address range, you may customize your own Xillybus IP core, download a bundle and integrate it with your project.

    You my add another /dev/xillybus_something interface with your own specifications or change the existing one.

    See http://xillybus.com/ipfactory/

    Regards,
       Eli

  • 0

    So there isn't any built in way to connect to the read_32 or write_32?

  • 0

    I've looked at the IP core stuff and they seem like a much better alternative to just modifying xillydemo like I am now.  However, I'm confused if I can have them be the only component included in the bit file and still have my PS start up and be able to access xillinux.  xillydemo seems to have many extra things that allow the PS to run with xillinux.  Can I just create an IP core in the manner you specified and attact my signals or instantiate the IP core in my vhdl or verilog file and customize it for the computations I want to perform then just generate a BIT file?  This seems too easy, is there any documentation I can look at like a tutorial that goes through this process or better explains what needs to be in the BIT file for the PS to boot with xillinux?  Thanks!

  • 0

    I suggest just following the flow on the site. The readme file in the bundle you'll download explains what to do with it. You will not trash the ISE project you already have, but rather replace some files and modify it slightly.

    There are no changes necessary on the host's side. The new Xillybus device files will be automatically detected.

    Section 5.1 of the "Getting started with Xillinux for Zynq-7000 EPP" guide discusses changes in the logic. But to make a long story short, you should reimplement the bitfile, generate the boot.bin file using the new bitfile, and then copy the latter to the SD card. And you're done.

    And yes, it's easy.

    Regards,
       Eli

  • 0

    So I just create a 32 bit register through the IP like the mem_8 but a mem_32 and then write to it just like the mem_8?  That sounds too perfect.  Why can't I send things through the read_32 without commenting out the line in the fifo that also writes to read_32 (due to the multiple driver errors I can't write to read_32 and have the fifo write to it)

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    I think there were two questions there. As for mem_32, just go ahead. I don't know what you expect to happen, but let's see how it works out for you.

    As for the read_32 issue, as any signals in an HDL language, they can have only one driver (except for tristates, but who uses them?). So obviously, if you want to write to that FIFO, that has to come instead of the loopback that the demo bundle comes with.

    You could always add another pair of streams in the IP Core Factory if you want to keep the loopback. Or you could write some logic to multiplex the two sources (yours and the loopback), but I really wonder why you'd like to do that.

    So it all comes down to trying out a custom core. Have fun!

       Eli

  • 0

    Works perfectly!  Follow the instructions in the readme and it let me write my 32 bit info to the terminal very easily, I just changed mem_8 to mem_32 so that I could keep the xillydemo file the same.  Thanks for all of the help!