Hi all,
I am unable to change cache policy of the ARM in Xilinx Zynq platform.
I have a working design of the ACP port and would like to monitor static) the cache behavior to determine when I should switch from ACP to HP for different frame sizes for a video application. I have gotten the PMU event monitors and the PL310 event monitors working on bare metal application.
The ACP read monitoring was easier. As the all the DMA reads from ACP can be measured as cache read hits from PMU event monitors.
The ACP writes are tricky as the it depends on the cache policy. I didn't observe any events on both PMU and PL310 event monitors. It seems that the cache writes are Write-Back, no Write-Allocate policy from MMUTable from the below statement. I would like to make it write through policy and observe the cache hits on l2 cache PL310 event monitor.
The data that is placed on HIgh OCM region is made cacheable using the following commands which modify MMUtable.
// S=b1 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1
//Xil_SetTlbAttributes(0xFFF00000,0x14c0e);
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf (Page 78). C=1, B=1 determines that Write-Back, no Write-Allocate.
When I change it to write through C=1, B=0 policy, the program hangs. Is it because of the translation_table.s which has the following setting for the same region.
/* 256K OCM when mapped to high address space
* inner-cacheable */
.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
Is there any guidelines any changing this policy settings? maybe I need to disable the MMU, set the policy and re-enable the MMU or something like that. though it's not specified. the example at the below link doesn't not do that though http://www.xilinx.com/support/answers/50826.htm.
Is there any register to check why the processor hanging?
Thanks in advance.
