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Xillinux 1.0 Error at the beginning

e14 Contributor

Hello everybody ,

I'm starting to use the zedboard and I want to install Xillinux 1.0 on it.But I got some errors at the beginning of the installation.

In fact i'm going on
http://xillybus.com/xillinux/
and I download the boot image creation kit and the SD card image
Well no problem for that.^^
I follow this to install Xillinux:
http://xillybus.com/downloads/doc/xillybus_getting_started_zynq.pdf

But when I try to Generate the Netlist (point 3.3 in xillybus_getting_started_zynq.pdf ) I got several errors that i didn't understand

ERROR:EDK:4073 - INSTANCE: processing_system7_0, PORT: GPIO_I, CONNECTOR:
   processing_system7_0_GPIO_I - 56 bit-width connector assigned to 64 bit-width
   port -
   C:Usersarnaudxillinux-eval-zedboard-1.0xillinux-eval-zedboard-1.0system
   system.mhs line 104
ERROR:EDK:4073 - INSTANCE: processing_system7_0, PORT: GPIO_O, CONNECTOR:
   processing_system7_0_GPIO_O - 56 bit-width connector assigned to 64 bit-width
   port -
   C:Usersarnaudxillinux-eval-zedboard-1.0xillinux-eval-zedboard-1.0system
   system.mhs line 104
ERROR:EDK:4073 - INSTANCE: processing_system7_0, PORT: GPIO_T, CONNECTOR:
   processing_system7_0_GPIO_T - 56 bit-width connector assigned to 64 bit-width
   port -
   C:Usersarnaudxillinux-eval-zedboard-1.0xillinux-eval-zedboard-1.0system
   system.mhs line 104
ERROR:EDK:440 - platgen failed with errors!


I'm on Windows 7 64bits and I use xillinx design suite 14.3

Thanks for help

  • 0

    I modified this file system.msh just near the stystem.xmp
    I replace this line :
    PORT processing_system7_0_GPIO = processing_system7_0_GPIO, DIR = IO, VEC = [53:0]
    buy this one :
    PORT processing_system7_0_GPIO = processing_system7_0_GPIO, DIR = IO, VEC = [63:0]

    And now I can generate my net list without error
    YEEEESSSSSS!...
    The next step regenerate fifo ok ! no problem
    But on the next Generate the bitstream in ISE, I got an error due to my modification I think :

    ERROR:Place:866 - Not enough valid sites to place the following IOBs:
       IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
       BIDIR, DRIVE_STR = 12
       tprocessing_system7_0_GPIO<60>
       tprocessing_system7_0_GPIO<63>
       tprocessing_system7_0_GPIO<62>
       tprocessing_system7_0_GPIO<61>
       tprocessing_system7_0_GPIO<58>
       tprocessing_system7_0_GPIO<57>
       tprocessing_system7_0_GPIO<56>
       tprocessing_system7_0_GPIO<59>
    ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

    Indeed it seems to be which one I add to generate the Netlist before
    So anyone got this problem before me ? did I fail when i download the file (10 times^^) ?

    thanks for help

  • 0 in reply to e14 Contributor

    Your download was fine, otherwise unzipping of the bundle would fail.

    The problem seems to be that ISE 14.3 runs a sanity check which ISE 14.2 doesn't care about, and fails on that check. The error you mention there has never appeared in ISE 14.2.

    This will be fixed at the next release of Xillinux, but for the time being I suggest starting it all over with ISE 14.2. Sorry about the bother.

       Eli

  • 0

    As pointed out above, I found the same problem when generate netlist in XPS 14.3.
    So I am trying the solve the problem and successed.
    Below I will try to explain HOW TO do it, and some experience of xilinx software is needed(don't be afraid, its simply and graphic).
    As mentioned in "xillybus_getting_started_zynq.pdf" part 3.3, we need to generate netlist and that is where the error occured.
    So we started from here, steps below:
    1.Open the system.xmp in system folder;
    2.Select update project, and next..next..finish, this will update ps_system from 14.2 to 14.3.
    3.In system assembbly view, table "zynq", left click the picture named "I/O Peripherals", and the "Zynq PS MIO Configuration" window shown up.
    4.Expand "GPIO", enable the "EMIO GPIO", set the IO nmuber as 56, then close the window.
    5.In system assembbly view, table "zynq", left click the picture named "Clock Generation", and the "Clock Wizard" window shown up.
    6.Expand the "PL Fabric Clocks" and change FCLK_CLK3 frequcncy to "62.500000", then OK to save your settings.
    7. Now you can "Generate Netlist" without error, and everything goes well for following steps.

  • 0 in reply to e14 Contributor

    It's nice to see that you overcame those obstacles. I would like to point out two things, though:

    (1) I can't see how making any change to FCLK_CLK3 is related. This clock isn't connected to anything.

    (2) It looks like the parameter you mention in your item 4 is new to ISE 14.3, and this is probably the reason it was assigned the default of 64.

    I'll look into this soon.

    Thanks,
       Eli

  • 0

    My OS is win7_64 and ISE version is 14.3.
    A new error occur when I try to generate netlist after step4 that told me the FCLK_CLK3 should be 62.500000.




  • 0

    The docs are now updated to reflect the solution mentioned above, regarding fixing the GPIO's width. It turns out that a new parameter in the processor's XML file for the GPIO pin count was added in ISE 14.3, and its default was set to 64. So this caused a conflict with the actual 56 pins used. Thanks.

    As for the FCLK3, I built the processor's netlist with no problem without doing anything related to that, so I suppose it has to do with some custom use of that clock. For a plain Xillinux kit, there is no need to touch FCLK3's frequency (but it doesn't hurt, since it isn't used anyhow).

       Eli

  • 0

    thank you very much for these solution I'm going to try it this morning.