Board used: picoZed board for Zynq7030 containing two ARM cores; cpu0 and cpu1.
I have a private APU watchdog in each cpu. cpu0 runs freeRTOS and cpu1 runs bare-metal. Each cpu is hooked to its own interrupt controller, XScuGic.
The problem is... when cpu0 watchdog expires, it resets the system as expected; meaning... it internally resets SRST line (or POR line?) and is able to boot load in QSPI mode or SD mode depending upon the boot pins on the board . However, when cpu1 watchdog expires, the system loses power and then just... hangs. It does not load FSBL from QSPI or SD.
Is there some extra setting freeRTOS or FSBL perform regarding watchdog and reset? Does freeRTOS do software reset (SRST) different from bare-metal? or does cpu0 have more privileges than cpu1?