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Ultra96-V2 Petalinunx boot error with Vivado custom Design

jpgoncalves

Hello,

How are you?

I am developing a linux application with Petalinux 2020.1 and need to add a custom FPGA design generated from Vivado using the Ultra96-V2 Board preset. The problem is that when i add any peripheral that use interrupts, my linux kernel boot hangs. Howerver, i can boot with a custom bitstream where I only added BLOCK RAM. With this design my kernel boot and a i can write/read from this RAM on FPGA with devmem tool.

This is my linux kernel booting logs when algo using an AXI TIMER IP from Vivado.

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.4.0-xilinx-v2020.1 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP Wed Oct 5 12:21:52 UTC 2022
[    0.000000] Machine model: Avnet Ultra96 Rev1
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[    0.000000] printk: bootconsole [cdns0] enabled
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x000000003ed40000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node rproc@3ed400000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 512 MiB at 0x000000005fc00000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.1
[    0.000000] percpu: Embedded 21 pages/cpu s48664 r8192 d29160 u86016
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Speculative Store Bypass Disable mitigation not required
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 515524
[    0.000000] Kernel command line:  earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 1512568K/2094848K available (11836K kernel code, 688K rwdata, 3676K rodata, 704K init, 518K bss, 57992K reserved, 524288K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq-xilinx: /amba/axi-interrupt-ctrl: num_irq=32, sw_irq=0, edge=0x0

I created the petalinux project using Ultra96-V2 2020.1 BSP.

After that, these are the steps i use to add my custom Vivado Design and generate my linux image

petalinux-config --get-hw-description <CUSTOM_HW_DIR_FILES>

petalinux-build -c avenet-image-minimal

petalinux-package --boot --force --u-boot --format BIN --fpga images/linux/system.bit --pmufw images/linux/pmufw.elf --fsbl images/linux/zynqmp_fsbl.elf

After that, i copy BOOT.bin and image.ub too BOOT partition of SD CARD and also copy rootfs.tar.gz to root partition of SD CARD.

  • Hello guys,

    I think that i found the problem. I don't no if this is the issue, but after removing it my board booted with my Vivado custom design. It seems that Avnet BSP for ultra96v2 board expect an interrupt controller inside the PL that is declared in the system_bsp.dtsi device tree file. This controller is used for the zocl, an AI accelerator ( i dont know a thing about it)  that send it interrupts to the controller. So, when i loaded my custom design by passing its fpga bitstream inside FSBL, when Linux try to init the interrupt controller driver, it will found an invalid memory location because i dont have the interrupt controller of Avnet BSP inside my design.

    So the workaround to boot my board was to just delete the interrupt controller and zocl nodes from Avnet BSP in my system-user.dtsi file as show below.

    This is the workaround i have done in my system-user.dtsi file to avoid chaging Avnet BSP

    &amba {

    /*Work around for interrupt driver init hanging linux boot*/
    /delete-node/axi-interrupt-ctrl;
    /delete-node/zyxclmm_drm;
    };

    These are the nodes in Avnet BSP (meta-avenet/recipes-bsp/device-tree/ultra96v2/system-bsp.dtsi) that seems to be causing the problem

    &amba {

    axi_intc_0: axi-interrupt-ctrl {
    #interrupt-cells = <2>;
    compatible = "xlnx,xps-intc-1.00.a";
    interrupt-controller;
    reg = <0x0 0xA0090000 0x0 0x1000>;
    xlnx,kind-of-intr = <0x0>;
    xlnx,num-intr-inputs = <0x20>;
    interrupt-parent = <&gic>;
    // connected at PS interrupt offset [6] (89+6=95)
    interrupts = <0 95 4>;
    };

    zyxclmm_drm {
    compatible = "xlnx,zocl";
    status = "okay";
    interrupt-parent = <&axi_intc_0>;
    interrupts = <0 4>, <1 4>, <2 4>, <3 4>,
    <4 4>, <5 4>, <6 4>, <7 4>,
    <8 4>, <9 4>, <10 4>, <11 4>,
    <12 4>, <13 4>, <14 4>, <15 4>,
    <16 4>, <17 4>, <18 4>, <19 4>,
    <20 4>, <21 4>, <22 4>, <23 4>,
    <24 4>, <25 4>, <26 4>, <27 4>,
    <28 4>, <29 4>, <30 4>, <31 4>;
    };
    };

    I hope that this solution help other people with the same problem because i found a lot of them on the internet but no possible solution. I want to hear from Avnet guys if my analysis is correct or if there another workaround. 

    Thanks for all!

    Att,

    João Paulo