xilinx-vdma 43000000.dma: reset timeout

I am using 7z020clg400(vivado2018.3 and petalinux2018) for camera data acquisition, using vivado exported hardware configuration to compile linux, there will be xilinx-vdma 43000000.dma: reset timeout exception information in the kernel startup phase.

dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330 
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 
xilinx-vdma 43000000.dma: reset timeout, cr 10006, sr 10001 
xilinx-vdma 43000000.dma: Reset channel failed xilinx-vdma 43000000.dma: Xilinx AXI VDMA Engine Driver Probed!!

The corresponding code location is：drivers\dma\xilinx\xilinx_dma.c

Automatically generated dts:

/ {
     amba_pl: amba_pl {
     #address-cells = <1>;
     #size-cells = <1>;
     compatible = "simple-bus";
     ranges ;
     axi_vdma_0: dma@43000000 {
          #dma-cells = <1>;
          clock-names = "s_axi_lite_aclk", "m_axi_s2mm_aclk", "s_axis_s2mm_aclk";
          clocks = <&clkc 15>, <&clkc 16>, <&misc_clk_0>;
          compatible = "xlnx,axi-vdma-6.3", "xlnx,axi-vdma-1.00.a";
          interrupt-names = "s2mm_introut";
          interrupt-parent = <&intc>;
          interrupts = <0 29 4>;
          reg = <0x43000000 0x10000>;
          xlnx,addrwidth = <0x20>;
          xlnx,flush-fsync = <0x1>;
          xlnx,num-fstores = <0x3>;
          dma-channel@43000030 {
               compatible = "xlnx,axi-vdma-s2mm-channel";
               interrupts = <0 29 4>;
               xlnx,datawidth = <0x10>;
               xlnx,device-id = <0x0>;
               xlnx,genlock-mode ;
               };
          };
     misc_clk_0: misc_clk_0 {
          #clock-cells = <0>;
          clock-frequency = <100000000>;
          compatible = "fixed-clock";
     };
};
};

vivado block design :

I checked for a few days and found no reason.

What could be the cause of the dma timeout?

Thank for the help.