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Ultra96-V2 constraints error

saraalonso

Hi!

I want to try the Ultra96-V2 board and I have made a design in Vivado where I just set the user leds to "0100". I have downloaded the constraints file from https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultra96-v2/ and following it I have added these lines to the io.xdc:

set_property PACKAGE_PIN AB4 [get_ports "leds[0]"];
set_property PACKAGE_PIN AA4 [get_ports "leds[1]"];
set_property PACKAGE_PIN Y5 [get_ports "leds[2]"];
set_property PACKAGE_PIN AA3 [get_ports "leds[3]"];

set_property IOSTANDARD LVCMOS18 [get_ports "leds[0]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[1]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[2]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[3]"];

But I get an error:

[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.

And 16 warnings like this:

[Common 17-55] 'set_property' expects at least one object. [io.xdc":1]

 

Does anyone know how to solve this?

  • The best way I know to create the XDC constraints for the I/Os of a Xilinx design in Vivado is to do the following:

     

    1. Open the RTL Analysis -> Open Elaborated Design - Schematic for the Vivado design.
      image
    2. Click on I/O Ports link in the top of the schematic window.  The elaborated schematic will always show the I/O ports in the design as Vivado sees them, not as you think you named them.
      image
    3. Then scroll through Find Results window to find your I/O and then constrain it to the Package Pin and I/O Std to match the schematics.
      image
    4. Save the constraints and Run Implementation again.

     

    --Tom

  • Based on the warning message, it sounds like your logic is being optimized away. You could try setting the output of the LEDs equal to the state of the Push Button. Or use a counting pattern.

    Bryan