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Ultra96 Hardware Design LVDS interface with high speed expansion connector

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LVDS interface with high speed expansion connector

jfsog over 6 years ago

Hello,

In the schematic of the Ultra96 board, I noticed that the VCCO_HP voltage value is 1.2V.

Then, I think that the use of LVDS interface is forbidden (for LVDS, the VCCO voltage have to be 1.8V).

Do you know if exist a possibility to use the LVDS interface with the high speed expansion connector ?

Thanks a lot.

0 jafoste4 over 6 years ago

Hi,
May I ask you to link the LVDS standard?
Thanks,
Josh
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0 jfsog over 6 years ago in reply to jafoste4

Hi Josh,

I noticed that in the Xilinx User Guide UG571 (v1.9) June 12, 2018, table 1-77. And also in the Xilinx Data Sheet DS925, Table 24.
The LVDS DC specifications gives the Vcco=1.8V only.
There is only one possibility to use another Vcco voltage value: when the internal differential termination is not used. But in Ultra96, I think there is no differential termination outside the FPGA and the internal termination must be set.
But may be, I have misunderstood something?
Thanks a lot.
Jeff
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0 jc2048 over 6 years ago

There's some information in this Xilinx suppport answer that might help you with getting an LVDS signal in to the FPGA at 1.2V (if you only need to input signals).

http://www.xilinx.com/support/answers/66786.html
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0 jfsog over 6 years ago in reply to jc2048

Hi Jon,

Thanks for the interesting link.
So I will consider the use of input DIFF_SSTL_12...
Now I have to verify the coupling LVDS driver / FPGA input.

Thanks again.
Jeff
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