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Ultra96 Hardware Design Problem of using PL part to access the GPIO
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Problem of using PL part to access the GPIO

pmuproject
pmuproject over 6 years ago

Hi,

I'm using Ultra96 with Ultrascale+ core. I followed this video (https://www.youtube.com/watch?v=NzWcRGjhfF8) to implement an example of using the PL part to access GPIO pin. But the codes on my device is not working. I used the oscillocope to check the voltage of the GPIO pin and the voltage is 0V. Below are the pictures of my system.

code.pngbodydiagram.pngcode.png

I'm using Vivado 2018.2.1. I connected my Ultra96 to my PC through JTAG. Then I used the "Program Device" button under hardware manager to program my Ultra96 after the bit stream generating. When I clicked "Program Device" button the picture below shows "there are nod debug cores". Is this meaning I can't use this way to program my device? Could anyone help me to check what is going wrong? Thanks!

warning.png

Regrads,

Hongqiang

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  • jafoste4
    0 jafoste4 over 6 years ago

    Hi Hong,

    What do your constraints look like? Where are you routing this through the PL? Is your setup the same as in the video you shared? You can safely ignore the no debug cores information.

     

    -Josh

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  • pmuproject
    0 pmuproject over 6 years ago in reply to jafoste4

    I also used the simulation to test the "led" signal which is my output port connected to HD_GPIO_0 pin. The simulation looks good but I still can't get the signal from oscillope.

    image

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  • pmuproject
    0 pmuproject over 6 years ago in reply to jafoste4

    I also used the simulation to test the "led" signal which is my output port connected to HD_GPIO_0 pin. The simulation looks good but I still can't get the signal from oscillope.

    image

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