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Has anyone used the Ultra96 rev 1 in the 2019.1 toolchain?

rich_dubielzig_rbt

Hi,

 

Avnet doesn't have 2019.1 support in its bdf git repo, but I noticed that the Ultra96 Rev 1 is now selectable from the Xilinx repo in Vivado 2019.1.  Does anyone here know what is needed to get it to boot?  Do you still need to do the pl_clk0 routing and PSU UART modifications as described in the Avnet tutorials?

 

-Rich

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    As a matter of fact, I just created an image for the Ultra96v1 from scratch.  I created the hardware project in Vivado, built it and exported it (including bit file).  I then created a petalinux project using zynqMP as the template instead of a source BSP.  I then did a petalinux-config --get-hw to incorporate the hardware project.

     

    I then (after a failed boot) changed the console to psu_uart_1 since uart0 is connected to the bluetooth module.  (petalinux-config then subsystem AUTO ... -> Serial settings -> primary stdin...).

     

    I built everything and tried to boot it.  It's hanging up when initializing the USB controllers.  As I typed this and was about to copy/past the end of the console log, I think I know the problem.  I use a non-volatile rootfs and I think it's not getting mounted.

     

    But, to answer your question, yes, 2019.1 seems to work without the clock modifications you mentioned... once I correct my error injections.

     

    Greg

  • 0 in reply to dyessgg

    I was able to get it running as well, up to the same point as you.  However, I was not able to see output until I tied the pl_clk0 signal to the fpd_aclk ports as described in section 8 of the Avnet tutorial.

     

    I am also starting off with an empty FPGA that will be employed later, which means that I had to make this fix to the device tree as well:

     

    https://forums.xilinx.com/t5/Open-Source-and-Community/Petalinux-2019-1-build-errors-for-ultra96v1/m-p/992383/highlight/…

     

    -Rich

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