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Ultra96 V2 hangs at psu_init (vivado 2018.2)

chris744

hi all,

 

i have just received a new ultra96 V2 board and i'm trying to do something

really simple. Just create a zynq block design and run the helloworld application.

i'm using vivado 2018.2. I have installed the Avnet Board Definition Files (BDF) :

 

ultra96v2 1.0

 

i have created a block design, inserted a zynq ultrascale+ ip, run block automation.

this is the first test i run when i get a new board.

 

but when i run the helloworld application, it hangs at :

image

 

any idea ?

 

ALEXANDRE Christophe

  • 0

    I have had the same problem. After some troubleshooting I found that the psu_init.tcl was hanging in the DDR configuration where it was trying to get information from the board. Someone from Avnet told me that they only saw that when the hardware configuration wasn't right, so I tried re-installing the board definition files. After that, I was able to get past the error. However, I never did get Hello World to come out the serial port. In my attempt to figure that out, I ended up creating a new project from the start and then it had the same problem with psu_init. I just re-installed the bdf files again and it seems to be loading correctly. Still nothing on the comm port, but at least I can get back to tracking that down. All I can say is "Good luck." If you find some success please post it back here.

  • 0

    The ultra96v2 1.0 BDF is the correct one. The psu_init should not hang. Are you downloading the bitstream to the PL first? Have you changed STDIN/OUT to uart1? Are you using the JTAG/UART Pod to access the USB-UART terminal?

    Bryan

     

  • 0 in reply to bhfletcher

    I've been getting the same issue since I've had my board, psu_init hangs basically every other time. When it hangs I have to kill it and restart the debug and then it will succeed. I've found a way around it by selecting system reset and program FPGA in the Debug configuration. I'm also seeing some other weird behavior:

     

    I get the following warning when building the bare metal BSP:

    translation_table.S:145:2: warning: #warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined" [-Wcpp]

    #warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"

      ^~~~~~~

     

    My application is also hanging if I add too much code (before it even hits the code I've added). I figured this was a stack/heap constraint but I've increased both sizes in lscript.ld from 0x2000 to 0x80000 and I'm still getting the hang.

     

    I believe these issues may all be related to DDR configuration, possibly in the board design files?

  • 0 in reply to gtaylormb

      wrote:

    My application is also hanging if I add too much code (before it even hits the code I've added). I figured this was a stack/heap constraint but I've increased both sizes in lscript.ld from 0x2000 to 0x80000 and I'm still getting the hang.

    Eh this was my own dumb fault, turns out this isn't an issue. But it's hard to see since breakpoints don't seem to work. Once the code is launched the debugger goes off on it's own. I'm using Centos 7.6 and Vivado 2019.1.

  • 0 in reply to tomc1394

    Try to change the sTD in/out interface in the BSP to ps uart 1 instead of uart 0.

    Open system.mss, --> click Modify this BSP's Settings --> Overview -> Standalone --> change stdin and stdout to psu_uart_1 instead of psu_uart_0, click OK and give a try image

  • 0 in reply to bhfletcher

    hi all,

     

    i'm using the JTAG/UART Pod to access the USB-UART terminal.

    i have changed STDIN/OUT to uart1.

     

    after some test, i have to :

     

    1) reset entire system,

    2) download the bistream to PL,

     

    then the psu_init runs correctly and the message displays in the terminal.

     

    you have to set this way if you want to run the application program as much as you want without powering off/on..

     

    image

     

    ALEXANDRE Christophe