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Is a schematic available for the AES-ACC-U96-JTAG?

ebconcannon

Is there any more documentation on the Ultra96 accessories? I need to know if I can connect 1.8 volts to the VREF of the UART on the AES-ACC-U96-JTAG.

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    We don’t share the JTAG/UART Pod schematics because of a license agreement with Xilinx. However, I can supply more information here.

     

    If an engineer wants to use the level translating function for the UART on the JTAG/UART pod:

    • Move position of JT1 to the 2-3 position
    • Apply the IO voltage to Pin 4 of J2
    • This Vref voltage will be translated via a SN74AVC2T245RSWR device to 3.3V, which is the IO interface with the USB-UART chip
      • universal low-voltage bidirectional translation between any of the 1.2 V, 1.5V, 1.8 V, 2.5 V, and 3.3 V voltage nodes

     

    So, yes, you can connect the JTAG/UART pod to a board that has 1.8V VCCO on the Xilinx device's UART IO, and it should work fine.

     

    Bryan

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  • 0

    We don’t share the JTAG/UART Pod schematics because of a license agreement with Xilinx. However, I can supply more information here.

     

    If an engineer wants to use the level translating function for the UART on the JTAG/UART pod:

    • Move position of JT1 to the 2-3 position
    • Apply the IO voltage to Pin 4 of J2
    • This Vref voltage will be translated via a SN74AVC2T245RSWR device to 3.3V, which is the IO interface with the USB-UART chip
      • universal low-voltage bidirectional translation between any of the 1.2 V, 1.5V, 1.8 V, 2.5 V, and 3.3 V voltage nodes

     

    So, yes, you can connect the JTAG/UART pod to a board that has 1.8V VCCO on the Xilinx device's UART IO, and it should work fine.

     

    Bryan

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