Hi,
I plan to design own mezzanine card that connect to 40pin expansion connector. There will be 20 IOs defined and used by FPGA side in my design. I can find 12 HD_GPIOs that can be used freely according to the schematics.
Regarding the left 8 IOs, can I redefine those MIOs as EMIOs and programmed by PL side?
Or I have to consider connect the card to 60pins' connector.