We have started shipping Ultra96-V2! There are a few minor issues which I will add to this discussion post. Any future Erratum that are found will also be posted here first, and then added to the Errata document posted under Ultra96-V2 Documentation.
Ultra96-V2 -- A power-down/reboot issue related to heavily loading the PL is being investigated. This was first noticed when executing the DPU at 666 MHz. Operating it at 500 MHz makes the problem go away. During operation when the failure happens, the board will spontaneously reboot.
This appears to be caused by a threshold being set to low on Pmic 0x13 CHD, which is the 0.85V, 3.0A, +VCCINT rail. When the current exceeds the Fault threshold, the Pmic disables that rail, causing Power Good to be deasserted. Since Power Good is tied to the MPSoC POR, the board resets. When the Pmic rail stabilizes, then Power Good is asserted, which deasserts POR, and then the board boots again. This is the intention of this design to prevent damage to a board if excessive current were drawn. However, our initial estimates using XPE and a heavily loaded PL test image appear to have been too pessimistic.
+VCCINT powers all of the following:
More information will be provided as we finish the verification of this issue.
Bryan
