Ultra96-V2 Board Definition File

In case you aren't aware, Avnet hosts our Board Definition Files on GitHub. You can find the basic Ultra96-V2 board definition at https://github.com/Avnet/bdf --> Ultra96v2/1.0. The instructions for installing the board definitions are included right on the GitHub page. Having the board definition installed will allow the Xilinx Vivado tool to create a project specifically for the Ultra96-V2 and apply the basic settings to make it work.

Bryan

louisprzebienda over 5 years ago

The part0_pins.xml file available at the Avnet hosts our Board Definition Files on GitHub for the Ultra96V2 board is in error. For example it list pins for 64 data lines of DDR but the interface is only 32-bit. See the following:
<pin index="98" name ="c0_ddr4_dq59" iostandard="POD12_DCI" loc="L21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="99" name ="c0_ddr4_dq60" iostandard="POD12_DCI" loc="M20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="100" name ="c0_ddr4_dq61" iostandard="POD12_DCI" loc="L19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="101" name ="c0_ddr4_dq62" iostandard="POD12_DCI" loc="M19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="102" name ="c0_ddr4_dq63" iostandard="POD12_DCI" loc="N19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
In addition the pins listed do not correspond a sbva484 package. For example pin K19 does not exist
<pin index="25" name ="c0_ddr4_ba1" iostandard="SSTL12_DCI" loc="K19" output_impedance="RDRV_40_40" slew="FAST"/>
Is the correct part0_pins.xml available?
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