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UltraZed PSADC/GNDADC pin question

gge7

Hello

 

Thank you all for taking the time to read and answer my question. 

 

I've been reviewing the UltraZed SOM schematic and one of many questions came up.  One of them is the PSADC pin and GNDADC pin.

The GNDADC pin is attached to the GND_SYSMON net which in turn is attached to the main ground through a ferrite bead, FB2, for filtering.   The question becomes is the bypass capacitor, C103 which sits on the PSADC rail, attached to the wrong ground?  It is attached to the main ground and not the GND_SYSMON?  Is this a mistake  in the schematic or the design?  

Another question is on the board do you have a small plan for GND_SYSMON and then have the ferrite bead, FB2 connector this to the main ground?

Finally the PSADC pin is powered from the VCCO_PSIO power through a ferrite bead, FB5,  This is somewhat different from what Xilinx recommends in their UG580 document where both the PSADC and VCCADC pins are filtered through a ferrite bead from VCCAUX.  What was your reason for following your approach instead of the Xilinx UG580 recommendation?

Thank you

Gary

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    Hello Gary,

    QUESTION 1 - I've been reviewing the UltraZed SOM schematic and one of many questions came up.  One of them is the PSADC pin and GNDADC pin. The GNDADC pin is attached to the GND_SYSMON net which in turn is attached to the main ground through a ferrite bead, FB2, for filtering.   The question becomes is the bypass capacitor, C103 which sits on the PSADC rail, attached to the wrong ground?  It is attached to the main ground and not the GND_SYSMON?  Is this a mistake in the schematic or the design? 

    ANSWER - This would be something we overlooked in the design. C102/C103/C106 would have been better served tied to GND_SYSMON. 

     

    QUESTION 2 - Another question is on the board do you have a small plan for GND_SYSMON and then have the ferrite bead, FB2 connector this to the main ground?

    ANSWER – The is a plane cutout on one of the GND planes that represents GND_SYSMON. You will see FB2 placed just to the right of the MPSoC which ties the larger GND plane to GND_SYSMON.

     

    QUESTION 3 - Finally the PSADC pin is powered from the VCCO_PSIO power through a ferrite bead, FB5,  This is somewhat different from what Xilinx recommends in their UG580 document where both the PSADC and VCCADC pins are filtered through a ferrite bead from VCCAUX.  What was your reason for following your approach instead of the Xilinx UG580 recommendation?

    ANSWER: This may be different from what Xilinx may have described in UG580, but it is still a sufficient solution. The PL SYSMON source is VCCAUX and the VCCADC is a filtered version of the VCCAUX rail. The PSAUX source is VCCO_PSIO and the PSADC is a filtered version of that PSAUX rail. A reason to separate the PSADC from the PLADC was Avnet’s support of the different available power modes. 

    --Josh

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    Hello Gary,

    QUESTION 1 - I've been reviewing the UltraZed SOM schematic and one of many questions came up.  One of them is the PSADC pin and GNDADC pin. The GNDADC pin is attached to the GND_SYSMON net which in turn is attached to the main ground through a ferrite bead, FB2, for filtering.   The question becomes is the bypass capacitor, C103 which sits on the PSADC rail, attached to the wrong ground?  It is attached to the main ground and not the GND_SYSMON?  Is this a mistake in the schematic or the design? 

    ANSWER - This would be something we overlooked in the design. C102/C103/C106 would have been better served tied to GND_SYSMON. 

     

    QUESTION 2 - Another question is on the board do you have a small plan for GND_SYSMON and then have the ferrite bead, FB2 connector this to the main ground?

    ANSWER – The is a plane cutout on one of the GND planes that represents GND_SYSMON. You will see FB2 placed just to the right of the MPSoC which ties the larger GND plane to GND_SYSMON.

     

    QUESTION 3 - Finally the PSADC pin is powered from the VCCO_PSIO power through a ferrite bead, FB5,  This is somewhat different from what Xilinx recommends in their UG580 document where both the PSADC and VCCADC pins are filtered through a ferrite bead from VCCAUX.  What was your reason for following your approach instead of the Xilinx UG580 recommendation?

    ANSWER: This may be different from what Xilinx may have described in UG580, but it is still a sufficient solution. The PL SYSMON source is VCCAUX and the VCCADC is a filtered version of the VCCAUX rail. The PSAUX source is VCCO_PSIO and the PSADC is a filtered version of that PSAUX rail. A reason to separate the PSADC from the PLADC was Avnet’s support of the different available power modes. 

    --Josh

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