Hello,
I have followed the UltraZed EG Starter Kit Tutorial (for the 2016.4 Vivado version) to recreate the demo project, everything's OK, I am able to synthese and implement the design but when I open the implemented design there are no DDR and MIO I/O mapped to any pads!!
When I generate the block design there is no DDR port (in a Zynq 7000 project this DDR port appears), so the wrapper has no DDR interface, and then the design doesn't contains DDR interface!
Where are those DDR and MIO signals defined in the project? Not in any xdc file...is it normal that the DDR port isn't in the BD?
Thank you, Christophe
