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Difficulty triggering PL outputs

chuffine

image

I am not getting any response from the PL outputs on the Ultrazed I/O Carrier and provided constraints file. I am running a PWM demo that appears to work, but gives no output. I added a constant feeding directly to an LED output, but nothing seems to work. What am I doing wrong?

Vivado block diagram

https://imgur.com/a/y0cn5

  • 0

    Hello,

    I believe your naming conventions are off for your constraints.

    Please run the following tcl commands and send me the results

     

    1.       This generates all the valid and invalid constraints present in your design – You may need to modify the file path

    a.       write_xdc -no_fixed_only -constraints all C:/Data/design.xdc

    2.       This writes only the invalid constraints – You may need to modify the file path

    a.       write_xdc -constraints invalid C:/Data/bad_constraints.xdc

     

    Thanks,

    Josh

  • 0
     
    ####################################################################################
    # Generated by Vivado 2017.4 built on 'Fri Dec 15 20:55:39 MST 2017' by 'xbuild'
    # Command Used: write_xdc -no_fixed_only -constraints all C:/Users/chuffine/Desktop/design.xdc
    ####################################################################################
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_0_0_board.xdc'
    ####################################################################################
     
    #--------------------Physical Constraints-----------------
     
    set_property BOARD_PART_PIN GPIO_DIP_SW0 [get_ports {dip_switches_8bits_tri_i[0]}]
    set_property PACKAGE_PIN P3 [get_ports {dip_switches_8bits_tri_i[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[0]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW1 [get_ports {dip_switches_8bits_tri_i[1]}]
    set_property PACKAGE_PIN P2 [get_ports {dip_switches_8bits_tri_i[1]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[1]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW2 [get_ports {dip_switches_8bits_tri_i[2]}]
    set_property PACKAGE_PIN N1 [get_ports {dip_switches_8bits_tri_i[2]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[2]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW3 [get_ports {dip_switches_8bits_tri_i[3]}]
    set_property PACKAGE_PIN P1 [get_ports {dip_switches_8bits_tri_i[3]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[3]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW4 [get_ports {dip_switches_8bits_tri_i[4]}]
    set_property PACKAGE_PIN J7 [get_ports {dip_switches_8bits_tri_i[4]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[4]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW5 [get_ports {dip_switches_8bits_tri_i[5]}]
    set_property PACKAGE_PIN J6 [get_ports {dip_switches_8bits_tri_i[5]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[5]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW6 [get_ports {dip_switches_8bits_tri_i[6]}]
    set_property PACKAGE_PIN L7 [get_ports {dip_switches_8bits_tri_i[6]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[6]}]
     
    set_property BOARD_PART_PIN GPIO_DIP_SW7 [get_ports {dip_switches_8bits_tri_i[7]}]
    set_property PACKAGE_PIN K7 [get_ports {dip_switches_8bits_tri_i[7]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {dip_switches_8bits_tri_i[7]}]
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_rst_ps8_0_99M_0_board.xdc'
    ####################################################################################
     
    #--------------------Physical Constraints-----------------
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_1_0_board.xdc'
    ####################################################################################
     
    #--------------------Physical Constraints-----------------
     
    set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports {led_8bits_tri_o[0]}]
    set_property PACKAGE_PIN R7 [get_ports {led_8bits_tri_o[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[0]}]
     
    set_property BOARD_PART_PIN GPIO_LED_1_LS [get_ports {led_8bits_tri_o[1]}]
    set_property PACKAGE_PIN T5 [get_ports {led_8bits_tri_o[1]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[1]}]
     
    set_property BOARD_PART_PIN GPIO_LED_2_LS [get_ports {led_8bits_tri_o[2]}]
    set_property PACKAGE_PIN T7 [get_ports {led_8bits_tri_o[2]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[2]}]
     
    set_property BOARD_PART_PIN GPIO_LED_3_LS [get_ports {led_8bits_tri_o[3]}]
    set_property PACKAGE_PIN T4 [get_ports {led_8bits_tri_o[3]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[3]}]
     
    set_property BOARD_PART_PIN GPIO_LED_4_LS [get_ports {led_8bits_tri_o[4]}]
    set_property PACKAGE_PIN T3 [get_ports {led_8bits_tri_o[4]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[4]}]
     
    set_property BOARD_PART_PIN GPIO_LED_5_LS [get_ports {led_8bits_tri_o[5]}]
    set_property PACKAGE_PIN U2 [get_ports {led_8bits_tri_o[5]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[5]}]
     
    set_property BOARD_PART_PIN GPIO_LED_6_LS [get_ports {led_8bits_tri_o[6]}]
    set_property PACKAGE_PIN U6 [get_ports {led_8bits_tri_o[6]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[6]}]
     
    set_property BOARD_PART_PIN GPIO_LED_7_LS [get_ports {led_8bits_tri_o[7]}]
    set_property PACKAGE_PIN U5 [get_ports {led_8bits_tri_o[7]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {led_8bits_tri_o[7]}]
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_2_0_board.xdc'
    ####################################################################################
     
    #--------------------Physical Constraints-----------------
     
    set_property BOARD_PART_PIN GPIO_PUSH_SW0 [get_ports {push_buttons_3bits_tri_i[0]}]
    set_property PACKAGE_PIN R1 [get_ports {push_buttons_3bits_tri_i[0]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {push_buttons_3bits_tri_i[0]}]
     
    set_property BOARD_PART_PIN GPIO_PUSH_SW1 [get_ports {push_buttons_3bits_tri_i[1]}]
    set_property PACKAGE_PIN L2 [get_ports {push_buttons_3bits_tri_i[1]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {push_buttons_3bits_tri_i[1]}]
     
    set_property BOARD_PART_PIN GPIO_PUSH_SW2 [get_ports {push_buttons_3bits_tri_i[2]}]
    set_property PACKAGE_PIN K2 [get_ports {push_buttons_3bits_tri_i[2]}]
    set_property IOSTANDARD LVCMOS18 [get_ports {push_buttons_3bits_tri_i[2]}]
     
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_zynq_ultra_ps_e_0_0.xdc'
    ####################################################################################
     
    ##############################PS XDC#########################################
    ############################################################################
    ##
    ##  Xilinx, Inc. 2006            www.xilinx.com
    ############################################################################
    ##  File name :       psu_constraints.xdc
    ##
    ##  Details :     Constraints file
    ##                    FPGA family:       zynq
    ##                    FPGA:              PROD-1
    ##                    Device Size:       xczu3eg
    ##                    Package:           sfva625
    ##                    Speedgrade:        -1
    ##
    ##
    ############################################################################
    ############################################################################
    ############################################################################
    # Clock constraints                                                        #
    ############################################################################
    current_instance design_1_i/zynq_ultra_ps_e_0/U0
    create_clock -period 10.000 -name clk_pl_0 [get_pins {PS8_i/PLCLK[0]}]
     
     
     
    current_instance -quiet
    set_property DONT_TOUCH true [get_cells design_1_i/zynq_ultra_ps_e_0/U0/PS8_i]
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_0_0.xdc'
    ####################################################################################
     
    # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
    #
    # This file contains confidential and proprietary information
    # of Xilinx, Inc. and is protected under U.S. and
    # international copyright and other intellectual property
    # laws.
    #
    # DISCLAIMER
    # This disclaimer is not a license and does not grant any
    # rights to the materials distributed herewith. Except as
    # otherwise provided in a valid license issued to you by
    # Xilinx, and to the maximum extent permitted by applicable
    # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    # (2) Xilinx shall not be liable (whether in contract or tort,
    # including negligence, or under any other theory of
    # liability) for any loss or damage of any kind or nature
    # related to, arising under or in connection with these
    # materials, including for any direct, or any indirect,
    # special, incidental, or consequential loss or damage
    # (including loss of data, profits, goodwill, or any type of
    # loss or damage suffered as a result of any action brought
    # by a third party) even if such damage or loss was
    # reasonably foreseeable or Xilinx had been advised of the
    # possibility of the same.
    #
    # CRITICAL APPLICATIONS
    # Xilinx products are not designed or intended to be fail-
    # safe, or for use in any application requiring fail-safe
    # performance, such as life-support or safety devices or
    # systems, Class III medical devices, nuclear facilities,
    # applications related to the deployment of airbags, or any
    # other applications that could lead to death, personal
    # injury, or severe property or environmental damage
    # (individually and collectively, "Critical
    # Applications"). Customer assumes the sole risk and
    # liability of any use of Xilinx products in Critical
    # Applications, subject only to applicable laws and
    # regulations governing limitations on product liability.
    #
    # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    # PART OF THIS FILE AT ALL TIMES.
     
    current_instance design_1_i/axi_gpio_0/U0
    set_false_path -to [get_pins -hier *cdc_to*/D]
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_rst_ps8_0_99M_0.xdc'
    ####################################################################################
     
     
    # file: design_1_rst_ps8_0_99M_0.xdc
    # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
    #
    # This file contains confidential and proprietary information
    # of Xilinx, Inc. and is protected under U.S. and
    # international copyright and other intellectual property
    # laws.
    #
    # DISCLAIMER
    # This disclaimer is not a license and does not grant any
    # rights to the materials distributed herewith. Except as
    # otherwise provided in a valid license issued to you by
    # Xilinx, and to the maximum extent permitted by applicable
    # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    # (2) Xilinx shall not be liable (whether in contract or tort,
    # including negligence, or under any other theory of
    # liability) for any loss or damage of any kind or nature
    # related to, arising under or in connection with these
    # materials, including for any direct, or any indirect,
    # special, incidental, or consequential loss or damage
    # (including loss of data, profits, goodwill, or any type of
    # loss or damage suffered as a result of any action brought
    # by a third party) even if such damage or loss was
    # reasonably foreseeable or Xilinx had been advised of the
    # possibility of the same.
    #
    # CRITICAL APPLICATIONS
    # Xilinx products are not designed or intended to be fail-
    # safe, or for use in any application requiring fail-safe
    # performance, such as life-support or safety devices or
    # systems, Class III medical devices, nuclear facilities,
    # applications related to the deployment of airbags, or any
    # other applications that could lead to death, personal
    # injury, or severe property or environmental damage
    # (individually and collectively, "Critical
    # Applications"). Customer assumes the sole risk and
    # liability of any use of Xilinx products in Critical
    # Applications, subject only to applicable laws and
    # regulations governing limitations on product liability.
    #
    # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    # PART OF THIS FILE AT ALL TIMES.
     
    current_instance -quiet
    current_instance design_1_i/rst_ps8_0_99M/U0
    set_false_path -to [get_pins -hier *cdc_to*/D]
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_1_0.xdc'
    ####################################################################################
     
    # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
    #
    # This file contains confidential and proprietary information
    # of Xilinx, Inc. and is protected under U.S. and
    # international copyright and other intellectual property
    # laws.
    #
    # DISCLAIMER
    # This disclaimer is not a license and does not grant any
    # rights to the materials distributed herewith. Except as
    # otherwise provided in a valid license issued to you by
    # Xilinx, and to the maximum extent permitted by applicable
    # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    # (2) Xilinx shall not be liable (whether in contract or tort,
    # including negligence, or under any other theory of
    # liability) for any loss or damage of any kind or nature
    # related to, arising under or in connection with these
    # materials, including for any direct, or any indirect,
    # special, incidental, or consequential loss or damage
    # (including loss of data, profits, goodwill, or any type of
    # loss or damage suffered as a result of any action brought
    # by a third party) even if such damage or loss was
    # reasonably foreseeable or Xilinx had been advised of the
    # possibility of the same.
    #
    # CRITICAL APPLICATIONS
    # Xilinx products are not designed or intended to be fail-
    # safe, or for use in any application requiring fail-safe
    # performance, such as life-support or safety devices or
    # systems, Class III medical devices, nuclear facilities,
    # applications related to the deployment of airbags, or any
    # other applications that could lead to death, personal
    # injury, or severe property or environmental damage
    # (individually and collectively, "Critical
    # Applications"). Customer assumes the sole risk and
    # liability of any use of Xilinx products in Critical
    # Applications, subject only to applicable laws and
    # regulations governing limitations on product liability.
    #
    # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    # PART OF THIS FILE AT ALL TIMES.
     
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_axi_gpio_2_0.xdc'
    ####################################################################################
     
    # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
    #
    # This file contains confidential and proprietary information
    # of Xilinx, Inc. and is protected under U.S. and
    # international copyright and other intellectual property
    # laws.
    #
    # DISCLAIMER
    # This disclaimer is not a license and does not grant any
    # rights to the materials distributed herewith. Except as
    # otherwise provided in a valid license issued to you by
    # Xilinx, and to the maximum extent permitted by applicable
    # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    # (2) Xilinx shall not be liable (whether in contract or tort,
    # including negligence, or under any other theory of
    # liability) for any loss or damage of any kind or nature
    # related to, arising under or in connection with these
    # materials, including for any direct, or any indirect,
    # special, incidental, or consequential loss or damage
    # (including loss of data, profits, goodwill, or any type of
    # loss or damage suffered as a result of any action brought
    # by a third party) even if such damage or loss was
    # reasonably foreseeable or Xilinx had been advised of the
    # possibility of the same.
    #
    # CRITICAL APPLICATIONS
    # Xilinx products are not designed or intended to be fail-
    # safe, or for use in any application requiring fail-safe
    # performance, such as life-support or safety devices or
    # systems, Class III medical devices, nuclear facilities,
    # applications related to the deployment of airbags, or any
    # other applications that could lead to death, personal
    # injury, or severe property or environmental damage
    # (individually and collectively, "Critical
    # Applications"). Customer assumes the sole risk and
    # liability of any use of Xilinx products in Critical
    # Applications, subject only to applicable laws and
    # regulations governing limitations on product liability.
    #
    # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    # PART OF THIS FILE AT ALL TIMES.
     
    current_instance -quiet
    current_instance design_1_i/axi_gpio_2/U0
    set_false_path -to [get_pins -hier *cdc_to*/D]
     
     
     
     
    ####################################################################################
    # Constraints from file : 'design_1_auto_ds_0_clocks.xdc'
    ####################################################################################
     
    ###############################################################################################################
    # Core-Level Timing Constraints for axi_dwidth_converter Component "design_1_auto_ds_0"
    ###############################################################################################################
    #
    # This component is not configured to perform asynchronous clock-domain-crossing.
    # No timing core-level constraints are needed.
    # (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
     
     
    ####################################################################################
    # Constraints from file : 'xpm_cdc_async_rst.tcl'
    ####################################################################################
     
    # Scoped constraints for xpm_cdc_async_rst
    current_instance -quiet
    current_instance design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst
    set_false_path -through [get_ports -scoped_to_current_instance src_arst] -to [all_registers]
     
     
    # Scoped constraints for xpm_cdc_async_rst
    current_instance -quiet
    current_instance design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst
    set_false_path -through [get_ports -scoped_to_current_instance src_arst] -to [all_registers]
     
     
    # Scoped constraints for xpm_cdc_async_rst
    current_instance -quiet
    current_instance design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst
    set_false_path -through [get_ports -scoped_to_current_instance src_arst] -to [all_registers]
     
     
     
     
    # Vivado Generated miscellaneous constraints 
     
    #revert back to original instance
    current_instance -quiet
     
       
      ####################################################################################
      # Generated by Vivado 2017.4 built on 'Fri Dec 15 20:55:39 MST 2017' by 'xbuild'
      # Command Used: write_xdc -constraints invalid C:/Users/chuffine/Desktop/bad_constraints.xdc
      ####################################################################################
       
     
  • 0

    It doesn't seem to be pulling the constraints from the file I have included from the master user constraints here: http://zedboard.org/product/ultrazed-io-carrier-card

    Even though I have the file included https://i.imgur.com/41GV6K0.png marked active and "set as target constraints file".

  • 0

    Hi,

    It appears your naming conventions are different from what is specified in the constraints. Thus it is unable to find the port you are referencing. Please double check you are naming the ports the same as what is specified in the master constraints.

    --Josh

  • 0

    They look the same. Do you recieve any critical warings or errors when building your Vivado Design?

    --Josh

  • 0

    I receive a large number of critical warnings, entirely consisting of "[Common 17-55] 'set_property' expects at least one object." for every net I do not have a signal applied to, since I just have the full master constraint file active. 

    There are no other reported errors.

     
  • 0

    Try commenting out the nets you are not using in your constraint file and rebuilding your design.

    --Josh

  • 0

    I removed all constraints I am using to another file and disabled the master constraints. I no longer have the critical warnings, but still no change.

  • 0

    Are there demos for PL blinking with the ultrazed? I'm trying to find something to see where I'm going wrong, but all the demos are either too basic, using PS MIO or way too complex to sift out what I need to know.