XCZU3EG has no support for PCIe

I would like to use the PCIe interface on the UltraZed SOM and PCIe Carrier. However, I cannot find any documents or designs that reference this capability. Furthermore, Vivado does not allow me to select PCI IP for this part.

I created a Petalinux project using Avnet_UltraZed-3EG_PCIEC_2017_2_BSP. But this BSP does not contain a PCIe IP core.

Any help would be appreciated.

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0 drozwood90 over 8 years ago

Hello,

The XCZU3EG chip has support for PCIe 1.0 and 2.0 directly in the PS and PCIe Gen 4 in the PL. You can see this in the Xilinx Product selection guide, page 5:
https://www.xilinx.com/support/documentation/selection-guides/zynq-ultrascale-plus-product-selection-guide.pdf

For you to create a PCIe core, you will need something to read that memory space on the PC.
As for setting up the PCIe core, you need to only include that in the PS configuration or include that in the BD for the PL.

There are, as you pointed out, a few third party PCIe cores, but that is not necessary in the UltraScale+ as there are both PS and PL PCIe cores.

--Dan
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0 drozwood90 over 8 years ago

Hello,

The XCZU3EG chip has support for PCIe 1.0 and 2.0 directly in the PS and PCIe Gen 4 in the PL. You can see this in the Xilinx Product selection guide, page 5:
https://www.xilinx.com/support/documentation/selection-guides/zynq-ultrascale-plus-product-selection-guide.pdf

For you to create a PCIe core, you will need something to read that memory space on the PC.
As for setting up the PCIe core, you need to only include that in the PS configuration or include that in the BD for the PL.

There are, as you pointed out, a few third party PCIe cores, but that is not necessary in the UltraScale+ as there are both PS and PL PCIe cores.

--Dan
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