Hi,
I’m working actually on Ultrazed board (from Avnet IO Carrier Card) with a XCZU3EG engineering sample. I’m trying to get the Xilinx example “xaxidma_multichan_sg_int.c” to work but I have a problem. This code can be found there C:\Xilinx\SDK\2017.2\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_3\examples.
First, I’m using Vivado 2017.2 on Window10. Below, you can see my design with a loop back architecture (or not if it's not working), as the example requires.
<html><head><title>Jive SBS</title></head>
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<b>Error</b><br><font size="-1">
An general error occurred while processing your request.
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The program should transmit 2 packets from the DMA to the 2 FIFOs (Each packet is sent into a different channel). Then, read it back and compare if the data are the same.
So, the example doesn’t work. Either the program get stuck in an infinite loop or it’s fail with this message: "Failed test transmit not done, receive not done"
<html><head><title>Jive SBS</title></head>
<body><font face="arial,helvetica,sans-serif">
<b>Error</b><br><font size="-1">
An general error occurred while processing your request.
</font></font></body></html>
It's seems there are some problem with interrupt. For test my design, I try the exact same architecture with the same code on a Zedboard (Zynq-7000). The program work and “Successfully ran AXI DMA SG interrupt example”.
So, I’m wonder :
- If my design is good with the Ultrascale?
- Maybe there something to do more with it at the interruption level
- I don’t always have the same comportment when I run the code and that’s strange. I’m working on an engineering sample, that’s why?
- Does anybody already used the AXI DMA in multichannel mode on Ultrascale and encounter those problems?
- Do I have made a silly error somewhere else?
I continue my search for now. Thank you for your time,
Louis.
PS: I post the same thing on xilinx forum (with a litlle more details) there :
