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Ultrazed Hardware Design where to find "specific SOM's PS VBATT resistor"?
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Related

where to find "specific SOM's PS VBATT resistor"?

jonaszz
jonaszz over 8 years ago

Like mentioned in my last post, I try to implement a Secure Boot on the UltraZed. I need to get the +PS_VBATT working, because for some reasons, the keys gets lost when power-cycle to boot from QSPI or SD. After hours of searching, I found what might be the problem:

 

--- Sorry the image from the File Server doesn't get displayed correctly. It is from http://zedboard.org/sites/default/files/documentations/UltraZed_EG_SOM_Designers_Guide_v1_1.pdf on Page 79: +PS_VBATT_TEST

 

But as soon as one is solved, there is another: What is meant by "the specific SOM's PS VBATT resistor"? I can't find any user guide which provides information.

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  • jafoste4
    jafoste4 over 8 years ago +1
    Hi JonasZZ, The reference is to whether a SOM has a VBATT resistor in place or not. The UZ-EG SOM does not have the PS_VBATT resistor, but last year we weren't sure what the future may bring for the SOM…
  • jafoste4
    jafoste4 over 8 years ago +1
    To further clarify, Xilinx has this pin either a) powered or b) grounded if not used. The decision was to place all control of this pin on the carrier, whether it be Avnet's (which we always power the…
  • jafoste4
    jafoste4 over 8 years ago +1
    Hi Jonas, Everything looks good on your end. We have since removed the PS VBATT resistor comment from the Schematics in order to prevent confusion. Thanks, Josh
  • jafoste4
    0 jafoste4 over 8 years ago

    Hi JonasZZ,

    The reference is to whether a SOM has a VBATT resistor in place or not.  The UZ-EG SOM does not have the PS_VBATT resistor, but last year we weren't sure what the future may bring for the SOM.  If you are using an Avnet UZ-EG carrier, the voltage is already provided to you from the 1.8V power supply, from a user header, or from the LR44 battery if placed. If you are not using an Avnet carrier board, you will be responsible for connecting 1.8V to the JX3.46 pin. 

    --Josh

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  • jafoste4
    0 jafoste4 over 8 years ago

    To further clarify, Xilinx has this pin either a) powered or b) grounded if not used. The decision was to place all control of this pin on the carrier, whether it be Avnet's (which we always power the pin) or the customer's carrier. If you are using the Avnet carrier, then you should be able to measure  ~1.5V on JP3 pin 1 if you have a battery installed and the board is off. If the board is on, then you should be measuring ~1.8V. In either circumstance you should have key memory retention. If you don’t, then there may be something wrong with your carrier or SOM.

    --Josh

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  • jonaszz
    0 jonaszz over 8 years ago in reply to jafoste4

    Hi Josh,

    thanks for your reply. We are both talking about JP3 on the SOM, not on the Carrier Card, right? Because on the Carrier Card, I'm able to measure 1.5V on JP3 with a battery connected (board turned off) and 1.8 with VCCAUX connected (board turned on). But if I remove the Jumper on the SOM's JP3 I measure 0V in both cases!

     

    I'm also also to measure the correct Voltage on JX3.46, so the power is definitely passed on to the SOM.

     

    Jonas

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  • jafoste4
    0 jafoste4 over 8 years ago

    Hi Jonas,

    Everything looks good on your end.

    We have since removed the PS VBATT resistor comment from the Schematics in order to prevent confusion.

    Thanks,

    Josh 

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  • jonaszz
    0 jonaszz over 8 years ago in reply to jafoste4

    Thank you for your answer!

    So could you please confirm, that on the SOM JP1 has to be open open, JP2 and JP3 have to be installed in order to supply the BBRAM with 1.5V? is there any point on the SOM where is can measure this (besides JX3.46)? And considering the hardware, nothing else could cause the BBRAM to loose the key, when a LR44 battery is connected on the Carrier Card?

    I have spent many hours on this issue by now.

    Another weird thing about the security features of the UltraZed is, that in Vivado -> Edit Device Properties, the "Encryption" Tab isn't available. So how do you enable Bitstream encryption?

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  • jafoste4
    0 jafoste4 over 8 years ago

    Hi Jonas,

    From the SOM’s perspective, you don’t need anything shunted when talking about eFuse/Encryption technology in the UltraScale part. JP1 is PWR_DISABLE – You shunt this, the board doesn’t work. You don't need the PMBUS connected (JP2/JP3) unless you are monitoring the PMBUS from the MPSoC. I wouldn't think you would be doing this, but if you are then you would need the shunts(JP2/JP3) to make the connection.

    From the eFuse/Encryption standpoint, youcan look at the +PS_VBATT rail on the SOM at capacitor C100 on the SOM. The left side of the capacitor is the +PS_VBATT rail. You should be able to take care not to short this capacitor with C81 right next to it as the +VCCO_PSIO rail exists right across from the +PS_VBATT terminal on C100.

    If you need support on actually using the encryption features please utilize this document

    https://www.xilinx.com/support/documentation/application_notes/xapp1267-encryp-efuse-program.pdf

    If that document does not resolve you issue I am going to suggest you get in contact with your local Avnet FAE. If you would like to venture down that avenue please feel free to reach back out and I will help you to get in contact with them.

    Thanks,

    Josh

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