Why Zynq Ultrascale PS in Block Diagram has only 95 bits of EMIO?

Question

Hi,

I just enabled EMIO pins of Zynq ultrascale+ for my application. I was expecting it to have 96 bits ( 3 banks of 32 bits each), according to Zynq ultrascale+ architecture. But Why does block diagram shows only 95 bits of EMIO . I can see [0:94] and not [0:95]. Why is this? Ideally it must have 96 bits isnt?

Goutham

jafoste4 · Accepted Answer

Hi Goutham, I see what you mean. This appears to be a bug with the tool. You will need to open a web case on the Xilinx website to resolve your issue. https://www.xilinx.com/ --Josh