UltraZed DDR4

Question

Hello

Thank you again for your time.

Again reviewing the UltraZed SOM schematic and Hardware Design Guide I wanted to find out if when you laid out the DDR4 did your compensate for the pin package flight delays in the Micron DDR? I know you stated you did for the Zynq UltraScale+ Package but not sure about the DDR4 RAM?

If you did, did you calculate the flight delay times from the IBIS model using Xilinx's AR34174 method where by you use the SQRT of L*C of each pin shown in the IBIS model? Would that be a valid way?

Thank you again,

Gary

jafoste4 · Accepted Answer

Hello Gary,

QUESTION 1 - Again reviewing the UltraZed SOM schematic and Hardware Design Guide I wanted to find out if when you laid out the DDR4 did your compensate for the pin package flight delays in the Micron DDR? I know you stated you did for the Zynq UltraScale+ Package but not sure about the DDR4 RAM?

ANSWER - The DDR4 RAM package delay was not removed from the design. With that said, one could feasibly attempt to extract that data from the IBIS model, but it was shown during the prototype phase that the DDR4 implementation at the maximum performance of the MPSoC passed stress tests provided to Avnet by Xilinx.

QUESTION 2 - If you did, did you calculate the flight delay times from the IBIS model using Xilinx's AR34174 method where by you use the SQRT of L*C of each pin shown in the IBIS model? Would that be a valid way?

ANSWER - We did not include the DDR4 package delay in the interface calculation.