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Ultrazed Hardware Design EV7 SOM Power reduction ideas
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EV7 SOM Power reduction ideas

youngn111
youngn111 over 4 years ago

I have a custom carrier board that connects a number of peripherals to the EV7 SOM.  Our design is using too much power for our application, and we are running into thermal runaway issues that ultimately shut down our power supplies.  We have a few mechanical engineering ideas to help vent the power, but we also wish to reduce the power consumption.

 

So, I  am looking for tips on power reduction with the EV7 SOM.

We use the PL for the heavy lifting in the design, and for the most part... the CPU is not too busy (except for handling interrupts to the video drivers).

 

We are not using the USB3, GigE, eMMC, or PL DDR.  Looking at the SOM schematics, those devices have active-low resets with pullups and we have the PCA9654 configured as inputs on those nets, so they are not being held in reset.  I will make a software build to try to hold these in reset... In the past, I found that will often bring current consumption from mA to uA.

 

We are using Petalinux.  Are there options to auto-throttle the CPU(s)?  We can probably get away with a single core running at 600MHz.  Default, I believe, is for all (4) cores at 1.2GHz.

I recall reading a Xilinx AR at some point about flaky behavior unless the bootarg of cpuidle was set to zero (meaning no sleeping for the CPU).

 

Any other ideas?

 

Thank you.

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  • drozwood90
    drozwood90 over 4 years ago +1 suggested
    Hi there, We do not really get into the details of things like that. In some cases you actually cannot have these types of power saving features enabled and with our wide audience of users, it is hard…
  • drozwood90
    0 drozwood90 over 4 years ago

    Hi there,

     

    We do not really get into the details of things like that.  In some cases you actually cannot have these types of power saving features enabled and with our wide audience of users, it is hard to justify working on features that only a small group might use.

     

    That being said, you can take a look at the slew of documentation out there, such as WP466, WP451, as well as using best practices.  Such as using clock controls to turn off domains of logic when not being used.  This here would save you the most power if you are already working on the PS.

    You can also look at using low power MPSoC.  Avnet can produce custom SOMS that has the -L designator in the part number.  These use lower voltage rails.  These are custom orders so there are some hoops to jump through, but if it works for you that is another way.

    You can also do things in the PS as you suggest to reduce the power.

    Be careful and understand what you are changing, but an example is under the Clock Configuration page in Vivado:

    image

    Could be changed to:

    image

    You need to be careful and validate everything, but the tools seem to let you go down to 0.  This would save you power on those clocked items (I did not have the RPU in the first screen shot).

    If you changed the PetaLinux Kernel, you could likely tune out the other cores as well, as you suggested.

     

    A group that has done a LOT of work on this, especially around the UltraZed-EG and Ultra96 are Aggios.  https://www.aggios.com/

    I have not used their services myself, but they have some pretty aggressive power management capabilities.  Take a look at their YouTube channel.  They actually access the PMICS use that access to provide a more comprehensive power reduction.

    https://www.youtube.com/channel/UCHaOy23ETlImizuAyHIHd2Q

    I am personally not sure of how to disable other cores, but I can ping a colleague to see if he can assist.  I do know you can tune the frequencies and all of that is done in the Vivado portion.

     

    Again, usually our goals for most of our customers is fast fast fast!

     

    --Dan

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