Hello. Im trying to implement a SDI TX using SMPTE UHD-SDI TX SUBSYSTEM and UHD-SDI GT in UltraZed -EV SOM + CC.
I have some doubt about the CLK used.
This is my connection block. I read that a 148.5 CLK is needed, Seeing the User Guide of CC, its says:
"Clock Generator 2 – U6, IDT 8T49N241-048NLGI....
....
...
Default output frequencies:
– Output 0 – 100 MHz, HCSL, 3.3V, PCIe_REFCLK to PCIe port connector J14 with 33 ohm series termination resistors.
– Output 1 – 148.5 MHz, LVDS, 3.3V, AUX/Loopback, JX2 GTH_REFCLK[5]" PAGE 46
This is (in the XDC file):
set_property PACKAGE_PIN J7 [get_ports {GTH_REFCLK5_N}]
set_property PACKAGE_PIN J8 [get_ports {GTH_REFCLK5_P}]
But MY QUESTION IS:
This clk need to be the "CLK_IN_D" input of the Utility Buffer , then the output of this is the Input for intf_0_qpll_refclk_in or intf_0_sb_tx_clk ?
Im using this https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Blog-Implementing-the-UHD-SDI-TX-subsystem-in-a-TX-only/ba-p/1170471
as guide and VCU https://xterra2.avnet.com/xilinx/zedboard/ultrazed-ev/vcu-trd-ports/rdf0428-uz7ev-vcu-trd-2019-2 as my project.
Best,
Franco
