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FSBL Problems in Vitis

francaprgonz

Hello, I was working with Ultrazed fine. i could modify the avnet base proyect, execute in baremetal some examples ("hello world", my own examples with Video Test Pattern Generator,etc),

 

Yesterday i start to have problems using the board.

image

 

So i tried to work with SD card that used weeks before (and i was working).If i switch to start with SD, the FPGA doesnt program(led blue off).

If i program the FPGA with JTAG the LED turns blue ( programmed) but i cannot execute a "hello world" example. It says:




vitis Log:

image

----------------End of Script----------------

 

 

09:01:58 INFO : Launch script is exported to file '/home/ubuntu/workspace/2020_BASE/hello_system/_ide/scripts/debugger_hello-default.tcl'

09:02:11 INFO : Disconnected from the channel tcfchan#2.

09:02:12 INFO : Connected to target on host '127.0.0.1' and port '3121'.

09:02:12 INFO : Jtag cable 'Digilent JTAG-SMT2JTAG-SMT2 210251A510AE' is selected.

09:02:12 INFO : 'jtag frequency' command is executed.

09:02:12 INFO : Sourcing of '/tools/Xilinx/Vitis/2020.2/scripts/vitis/util/zynqmp_utils.tcl' is done.

09:02:12 INFO : Context for 'APU' is selected.

09:02:13 INFO : System reset is completed.

09:02:16 INFO : 'after 3000' command is executed.

09:02:16 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2JTAG-SMT2 210251A510AE" && level==0 && jtag_device_ctx=="jsn-JTAG-SMT2JTAG-SMT2-210251A510AE-14730093-0"}' command is executed.

09:02:27 INFO : Device configured successfully with "/home/ubuntu/workspace/2020_BASE/hello/_ide/bitstream/uz7ev_evcc_base.bit"

09:02:27 INFO : Context for 'APU' is selected.

09:02:27 INFO : Hardware design and registers information is loaded from '/home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/hw/uz7ev_evcc_base.xsa'.

09:02:27 INFO : 'configparams force-mem-access 1' command is executed.

09:02:27 INFO : Context for 'APU' is selected.

09:02:27 INFO : Boot mode is read from the target.

09:02:27 INFO : Context for processor 'psu_cortexa53_0' is selected.

09:02:27 INFO : Processor reset is completed for 'psu_cortexa53_0'.

09:02:28 INFO : The application '/home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/sw/ultrazed_base/boot/fsbl.elf' is downloaded to processor 'psu_cortexa53_0'.

09:02:28 INFO : 'set bp_2_28_fsbl_bp [bpadd -addr &XFsbl_Exit]' command is executed.

09:03:28 WARN : Exit breakpoint of FSBL (XFsbl_Exit) is not hit within allocated wait time of '60' seconds.

Note: To wait for a fixed amount of time specify the FSBL function as empty in launch configuration. Use 'IDE_FSBL_BP_HIT_WAIT_TIME' environment variable in launch configuration to modify the wait time (seconds).

Reason: timeout: target has not halted

09:03:28 INFO : 'bpremove $bp_2_28_fsbl_bp' command is executed.

09:06:28 INFO : ----------------XSDB Script----------------

connect -url tcp:127.0.0.1:3121

source /tools/Xilinx/Vitis/2020.2/scripts/vitis/util/zynqmp_utils.tcl

targets -set -nocase -filter {name =~"APU*"}

rst -system

after 3000

targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2JTAG-SMT2 210251A510AE" && level==0 && jtag_device_ctx=="jsn-JTAG-SMT2JTAG-SMT2-210251A510AE-14730093-0"}

fpga -file /home/ubuntu/workspace/2020_BASE/hello/_ide/bitstream/uz7ev_evcc_base.bit

targets -set -nocase -filter {name =~"APU*"}

loadhw -hw /home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/hw/uz7ev_evcc_base.xsa -mem-ranges [list {0x80000000 0xbfffffff} {0x400000000 0x5ffffffff} {0x1000000000 0x7fffffffff}] -regs

configparams force-mem-access 1

targets -set -nocase -filter {name =~"APU*"}

set mode [expr [mrd -value 0xFF5E0200] & 0xf]

targets -set -nocase -filter {name =~ "*A53*#0"}

rst -processor

dow /home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/sw/ultrazed_base/boot/fsbl.elf

set bp_2_28_fsbl_bp [bpadd -addr &XFsbl_Exit]

con -block -timeout 60

bpremove $bp_2_28_fsbl_bp

----------------End of Script----------------

XSCT Console:

initializing

  0%    0MB   0.0MB/s  ??:?? ETA

  5%    1MB   1.9MB/s  ??:?? ETA

10%    1MB   1.8MB/s  ??:?? ETA

15%    2MB   1.7MB/s  ??:?? ETA

20%    3MB   1.7MB/s  ??:?? ETA

25%    4MB   1.8MB/s  ??:?? ETA

29%    5MB   1.7MB/s  00:07 ETA

35%    6MB   1.7MB/s  00:06 ETA

39%    7MB   1.7MB/s  00:06 ETA

44%    8MB   1.7MB/s  00:06 ETA

48%    8MB   1.7MB/s  00:05 ETA

54%    9MB   1.7MB/s  00:04 ETA

58%   10MB   1.7MB/s  00:04 ETA

63%   11MB   1.7MB/s  00:03 ETA

68%   12MB   1.7MB/s  00:03 ETA

73%   13MB   1.7MB/s  00:02 ETA

77%   14MB   1.7MB/s  00:02 ETA

82%   15MB   1.7MB/s  00:01 ETA

87%   16MB   1.7MB/s  00:01 ETA

91%   16MB   1.7MB/s  00:00 ETA

97%   17MB   1.7MB/s  00:00 ETA

100%   18MB   1.7MB/s  00:10  

Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)

xsct%

Downloading Program -- /home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/sw/ultrazed_base/boot/fsbl.elf

section, .text: 0xfffc0000 - 0xfffd2613

section, .note.gnu.build-id: 0xfffd2614 - 0xfffd2637

section, .init: 0xfffd2640 - 0xfffd2673

section, .fini: 0xfffd2680 - 0xfffd26b3

section, .rodata: 0xfffd26c0 - 0xfffd2c27

section, .sys_cfg_data: 0xfffd2c40 - 0xfffd34b7

section, .mmu_tbl0: 0xfffd4000 - 0xfffd400f

section, .mmu_tbl1: 0xfffd5000 - 0xfffd6fff

section, .mmu_tbl2: 0xfffd7000 - 0xfffdafff

section, .data: 0xfffdb000 - 0xfffdc227

section, .sbss: 0xfffdc228 - 0xfffdc23f

section, .bss: 0xfffdc240 - 0xfffde77f

section, .heap: 0xfffde780 - 0xfffdeb7f

section, .stack: 0xfffdeb80 - 0xfffe0b7f

section, .dup_data: 0xfffe0b80 - 0xfffe1da7

section, .handoff_params: 0xfffe9e00 - 0xfffe9e87

section, .bitstream_buffer: 0xffff0040 - 0xfffffc3f

 

 

  0%    0MB   0.0MB/s  ??:?? ETA

71%    0MB   0.2MB/s  ??:?? ETA

100%    0MB   0.2MB/s  00:00  

Setting PC to Program Start Address 0xfffc0000

Successfully downloaded /home/ubuntu/workspace/2020_BASE/ultrazed_base/export/ultrazed_base/sw/ultrazed_base/boot/fsbl.elf

Info: Breakpoint 7 status:

   target 9: {Address: 0xfffd0854 Type: Hardware}

xsct% Info: Cortex-A53 #0 (target 9) Running

 

 

image


Im using the base prject's bitstream. (I was using it really well the days before).

 

Vivado detect the FPGA (and i can programm it also):



image


I really dont know what to do. I change USB cables, reset PC, its very weird. I have  JP1,JP2,JP3 OFF  IN ULTRAZED EV SOM ( NO jumper), JP20 (of CC)  in 2,3
I think the problem is in the processor .



Best,

FC

Parents
  • 0

    Hi there,

     

    Can you go back to a prebuilt known good working Avnet design, just to make sure there is nothing else in your hardware?

    If you are up to it, you can find the Avnet prebuilt files here:

    http://avnet.me/ZedSupport

    I suggest one of the Vitis Prebuilt examples, as you can just DD that to an SDCARD.  Personally, I use BalenaEtcher,  Regardless, if that works you have validated a LOT of things.

    login is root/root

    If that doesn't work, I would suggest looking at your SDCARD, then to other parts of the boot process.  If all that works, then we can start looking into your design.

     

    What I am trying to get to, there is so many things that could be causing this, it is good to start to eliminate issues by simply trying a known good design, then you can work from there adding / changing.

     

    --Dan

  • 0 in reply to drozwood90

    Hi daniel,

    As i said. Im using a prebuilt image for SD Card, (SD iN FAT32 mode)

    Also im using Prebuild project for Vivado ( to program with JTAG). I was using the same projects for 1 months,This is not the first time that i try to use it. That's why sound weird.

    Projects :https://github.com/avnet/hdl.git

    In 2020.2 Branch and "base" project. Not VCU.

  • 0 in reply to francaprgonz

    Hi there,

     

    Thanks for clarifying.  From your account above, it seemed you started with the prebuilt, then moved on to modifying things.  I am sorry I did not catch that you are back to using the base design.

    So, as I stated above, if you are using one of the prebuilt designs (not one you generated), the next thing I would check is your SDCARD.

    • Which prebuilt file are you using?
    • Are you using the UltraZed-EV Starter Kit?
    • If so, are you using the SDCARD that came with the KIT?
    • If not, have you checked the SDCARD Advice document that Avnet has?

    I can say that personally, I have run into strange boot issues with off brand SDCARDS.

     

    You posted an image of the boot jumpers, that is good that you checked them.  That is also a suggestion.  If you do not have those right, it does not matter what we discuss!  I generally have mine set to ON-OFF-OFF-OFF.

     

    As for the Branch/etc., we have been working in the 2020.2 branch.  You might also want to try using the tag instead of the branch.  Just in case.  As we work on the HDMI/VCU/Quadcam designs, we are not double checking the other projects since that has been tagged.  I am not saying this IS your issue, but good practice.  Instead of checking out the 2020.2 branch, you will want to check out the 2020p2_uz7ev_evcc_base_20210426_105325 tag

    Updated Designed By Avnet BSP & Platforms for v2020.2 tools, the clutter reduction edition!

     

    --Dan

  • 0 in reply to drozwood90
    • Which prebuilt file are you using?

    Im using the prebuilt image of 2019.2 (uzevevccvadd_2019_2.tar) that i used before to use the board for the first time.

    • Are you using the UltraZed-EV Starter Kit?

    Yes im using the Starter Kit and also im checking the Jumpers

    • If so, are you using the SDCARD that came with the KIT?

    Yes, im using the SanDisk 16GB in FAT32 mode and this structure:

    I want to clarify again that in SD Card mode the LED of FPGA is off. I use this SD Card mode a month ago and it works, but now is not working .
    The same for JTAG mode but i can program the FPGA so LED is on, but the Cortex is "dead" or not working.
    The last thing, 2 days ago all was working (SD Mode and JTAG mode), i work 1 month and everything (in terms of board) was working .image

     

    EDIT: I also try with this rdf0428-uz7ev-vcu-trd-2018-3/images/vcu_uz7ev_cc · rdf0428-zcu106-vcu-trd-2018-3 · Xilinx / ZedBoard / UltraZED-EV / avn…
    Nothing happend in the UART and FPGA LED is OFF

     

    I reinstall Vivado 2020.2. Also i try with 2019.2

    So the problem can be more Hardware problem than Software problem. Also maybe can be produce because one bad program cycle did it.

    Best,
    FC

Reply
  • 0 in reply to drozwood90
    • Which prebuilt file are you using?

    Im using the prebuilt image of 2019.2 (uzevevccvadd_2019_2.tar) that i used before to use the board for the first time.

    • Are you using the UltraZed-EV Starter Kit?

    Yes im using the Starter Kit and also im checking the Jumpers

    • If so, are you using the SDCARD that came with the KIT?

    Yes, im using the SanDisk 16GB in FAT32 mode and this structure:

    I want to clarify again that in SD Card mode the LED of FPGA is off. I use this SD Card mode a month ago and it works, but now is not working .
    The same for JTAG mode but i can program the FPGA so LED is on, but the Cortex is "dead" or not working.
    The last thing, 2 days ago all was working (SD Mode and JTAG mode), i work 1 month and everything (in terms of board) was working .image

     

    EDIT: I also try with this rdf0428-uz7ev-vcu-trd-2018-3/images/vcu_uz7ev_cc · rdf0428-zcu106-vcu-trd-2018-3 · Xilinx / ZedBoard / UltraZED-EV / avn…
    Nothing happend in the UART and FPGA LED is OFF

     

    I reinstall Vivado 2020.2. Also i try with 2019.2

    So the problem can be more Hardware problem than Software problem. Also maybe can be produce because one bad program cycle did it.

    Best,
    FC

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