I am designing a carrier card for the UltraZed SOM, and wanted to use a similar design for a reference clock for high-speed SERDES communication as the Avnet Carrier Card design here: https://www.avnet.com/opasdata/d120001/medias/docus/190/UZ-EV-CC-UG-ver1.pdf
Since page 43 of that guide mentions using the 8T49N241 (datasheet https://www.renesas.com/us/en/document/dst/8t49n241-datasheet) in LVDS configuration for one of its output clocks as the GTH reference clock, I thought I would use this component (or the newer 8T49N242).
However, I noticed that, in the LVDS specifications for the output clock in Table 8H of that datasheet, the minimum differential voltage swing of the clock signal is 200 mV, while, according to Table 97 of XIlinx UltraScale+ AC and DC switching characteristics document DS925 (link: https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf ), the minimum differential voltage swing of a GTH reference clock is 250 mV.
Is this not a problem? the minimum differential voltage swing of the clock generator is less than the minimum differential voltage swing required by the Xilinx MPSoC by 50 mV. Does this need to be remedied for reliability?
