USB 3.0 support on ultrazed 7ev board petalinux 2020.2

kumakichi over 3 years ago

Hi there,

We have a design implemented on ultrazed 7v board,

and we found usb 3.0 is not working.

# both usb2.0 and usb 3.0 hub can be found,

but when we insert usb memory, it is always mounted as an usb 2.0 device( new high speed device founded)

--------------------

Problem is that beside the design we implemented,

we also tried the xsa inside

uz7ev_evcc_base_2020_2.tar.gz

https://avtinc.sharepoint.com/teams/ET-Downloads/Shared%20Documents/Forms/AllItems.aspx?id=%2Fteams%2FET%2DDownloads%2FShared%20Documents%2Fprojects%2Fpublic%5Frelease&p=true&ga=1

but got no luck there

We even compare the device tree of

Out of Box Designs

UltraZed Out of Box Designs

and the one above(uz7ev_evcc_base_2020_2)

nothing is specially different between the configurtation of the device tree.

We also checked the dwc3 status in the debugfs, found that

1.Firmware that we built(USB3 not working):

[root@uz7ev-evcc-base-2020-2 fe200000.dwc3]$ cat ./link_state
Not available

2.Firware that comes with the som(Ultrazed 7ev in emmc),[USB3 working]

[root@uz7ev-evcc-base-2017 fe200000.dwc3]$ cat ./link_state
U0

---

I actually posted the same question in Xilinx forum but no one replys...

https://support.xilinx.com/s/question/0D52E000076tGbHSAU/usb-30-is-not-working-on-ultrazed-ev-board?language=en_US

If you know anything insufficient in what we have done please kindly contact me,

Thank you in advance for your help.

kuma

kumakichi over 3 years ago

Additional Information:

Somehow managed to get the dts fille from the emmc firmware(USB 3.0 fine)

and the one we made to test the usb 3.0(not working)

		#NotWorking
		
		
		usb0@ff9d0000 {
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			status = "okay";
			compatible = "xlnx,zynqmp-dwc3";
			reg = <0x0 0xff9d0000 0x0 0x100>;
			clock-names = "bus_clk", "ref_clk";
			power-domains = <0xc 0x16>;
			ranges;
			nvmem-cells = <0x11>;
			nvmem-cell-names = "soc_revision";
			clocks = <0x3 0x20 0x3 0x22>;
			xlnx,tz-nonsecure = <0x1>;
			xlnx,usb-polarity = <0x0>;
			xlnx,usb-reset-mode = <0x0>;
			phandle = <0x6a>;

			dwc3@fe200000 {
				compatible = "snps,dwc3";
				status = "okay";
				reg = <0x0 0xfe200000 0x0 0x40000>;
				interrupt-parent = <0x4>;
				interrupt-names = "dwc_usb3", "otg", "hiber";
				interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>;
				#stream-id-cells = <0x1>;
				iommus = <0xd 0x860>;
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,refclk_fladj;
				snps,enable_guctl1_resume_quirk;
				snps,enable_guctl1_ipd_quirk;
				snps,xhci-stream-quirk;
				dr_mode = "host";
				phy-names = "usb3-phy";
				snps,usb3_lpm_capable;
				phys = <0x13 0x4 0x0 0x2 0x18cba80>;
				maximum-speed = "super-speed";
				phandle = <0x6b>;
			};
		};

From Working EMMC

		usb0@ff9d0000 {
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			status = "okay";
			compatible = "xlnx,zynqmp-dwc3";
			reg = <0x00 0xff9d0000 0x00 0x100>;
			clock-names = "bus_clk\0ref_clk";
			power-domains = <0x2c>;
			ranges;
			nvmem-cells = <0x1f>;
			nvmem-cell-names = "soc_revision";
			clocks = <0x03 0x20 0x03 0x22>;
			xlnx,usb-reset = <0x2faf080>;

			dwc3@fe200000 {
				compatible = "snps,dwc3";
				status = "okay";
				reg = <0x00 0xfe200000 0x00 0x40000>;
				interrupt-parent = <0x04>;
				interrupts = <0x00 0x41 0x04 0x00 0x45 0x04>;
				#stream-id-cells = <0x01>;
				iommus = <0x0e 0x860>;
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,refclk_fladj;
				snps,enable_guctl1_resume_quirk;
				snps,enable_guctl1_ipd_quirk;
				snps,xhci-stream-quirk;
				dr_mode = "host";
				phy-names = "usb3-phy";
				snps,usb3_lpm_capable;
				phys = <0x2d 0x04 0x00 0x02 0x3197500>;
			};
		};