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UZ EV CC Example contains eight Processor System Resets, why?

brianmckee

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Everything else makes sense. LED controls, switch inputs, interrupt controller, etc.

I figure there has got to be a reason, but I'm new to Vivado and was hoping someone could explain.

Thanks in advance.

  • Looking at the block diagram and clock generator, it appears the base design sets up several reference clocks.  Each of these clocks has a corresponding reset block for all IP using that clock.  If you're not using those clocks, delete the corresponding reset block.

    This was a nice touch the Avnet engineers did for a base design!

  • Here's the simple explanation:

    When you have different clocks in a system, each clock has it's own clock period and it's own phase (relative to the other clocks) at any point in time. 

    Resetting a digital circuit requires a reset signal to be asserted for a minimum number of cycles, counted on the rising or falling edges (depending on design) of the clock that is running that digital block.

    Now Imagine you had one block running from a 1Mhz clock and another block running from a 100Mhz clock. And imagine they are sharing the same clock reset that is derived from the 100Mhz clock. Let's say your IPs running off these clocks require the reset circuit to be asserted for a minimum of 10 clock cycles.

    Now if you have the same reset source (derived from the 100Mhz clock) trying to reset both blocks, the block running at 100Mhz will see the 10 cycles of reset signal correctly, but your block running at 1Mhz will see the reset asserted for only 1 clock (at best) or won't see it asserted at all (depending on when it's sampled) because of the much longer clock period. 

    You can imagine phase differences in clocks can result in similar issues. 

    So to overcome all of these issues, you create a reset source derived from EACH clock, and anything that uses a particular clock can then use the correponding reset block.

    Hope that explanation was somewhat intuitive.

    -Saad

  • in reply to saadtiwana_int

    Thanks for taking the time to post such a thorough answer. I really appreciate it.