Vitis - How to do I fix this boot / load error ?

export VITIS_FSBL_EXIT_TIMEOUT=60000 did not fix the problem. I tried VItis 2024.1 and 2023.2 and get the same results. I am using the Avnet UltraZed-EV board. When I create the platform I selected the zcu102 hardware design. There is a zed selection but not an ultrazed. Will the zcu102 hardware design work with the UltraZed-EV board ?

There are BSPs on this shared site that you can try: 

Engineering & Technology - Documentation - public_release - All Documents

Also here on Avnet GITHUB:

Avnet · GitHub

Are there simple exact instructions on how to create and debug a "Hello World" application on the UltraZed-EV board using Window 11 ?

MicroZed Chronicles has examples of this:

https://adaptivesupport.amd.com/s/article/747681?language=en_US

https://adaptivesupport.amd.com/s/article/749406?language=en_US

You can simply target the UltraZed-EV Board Definition Files for this.that are built into Vivado 2022 and on.

Thank you for the information but I still cannot get a simple "Hello World" application to work on the UltraZed-EV board using Window 11 and Vitis 2024.1 or 2023.2 ? The main link does not work and there is no clue how to use the other information. Is it possible for me to create a new thread and provide a link to the screen shots that show what I have done ? It should be a very simple process.

It is a relatively easy process. Here is the hardware generation process for Vivado.

1) Create a new RTL project.

2) Select the UltraZed-EV / EV Carrier Card Board (It is part of the Xilinx Board Store)

3) Create a block design and add the MPSoC IP.

4) Run Block Automation to Apply the BOARD PRESET.

5) Connect the FPD_ACLK ports to the PL_CLK0 ports - this is not automated.

6) Generate the BLOCK DESIGN from IP Integrator

7) When BLOCK DESIGN GENERATION is complete, generate the TOP LEVEL file and let Vivado AUTO MANAGE it. This is done by selecting the BD (block design) from the SOURCE window and right clicking on CREATE HDL WRAPPER.

8) From here you should be able to select GENERATE BITSREAM from the PROGRAM and DEBUG section of the FLOW NAVIGATOR.

At this point you have a valid HARDWARE DESIGN that you can export to VITIS (SDK).

I assume you were successful into getting to this point?

I will follow with the Vitis Flow shortly.

The Vitis Flow 2024.1: 

1) From Vivado - Export Hardware from the FILE MENU (EXPORT -> EXPORT HARDWARE). I typically always include the BITSTREAM. This generates the HDF/XSA which is a file used by Vitis.

2) You could use the Vivado tool to launch the VITIS IDE at this point., It's in the TOOLS MENU (LAUNCH VITIS IDE).

3) Create or point to a WORKSPACE for this project.

4) Create a PLATFORM COMPONENT using the XSA file generated by Vivado.- Target STANDALONE OS. This creates the BSP for use with the applications.

5) Create an APPLICATION COMPONENT - for this you can naviage the platform to the DRIVERS section and find the PSU_UART_0 driver. From within that DRIVER window all the way to the right is IMPORT EXAMPLES. You should be able to generate the HELLO WORLD example there.

6) BUILD both the PLATFORM and the HELLO WORLD APPLICATION.  You shouldn't see any PROBLEMS for either.

7) At this point you should be ready to target the HARDWARE. You will need to have the UART USB port connected to a PC with a terminal on it. The terminal should be set to the appropriate COM port with the appropriate settings: 115200. There are two COM ports associated with the EV Carrier Card. You will need to determine the proper one.

8) Don't forget your JTAG cable.

8) Power on the SOM/Carrier Card and from within Vitis you should be able to select RUN (RUN on HARDWARE) and get the HELLO WORLD to program over JTAG to the MPSoC.

9) You should see HELLO WORLD on the TERMINAL.

10) Next would be to build a BOOT IMAGE that you can program to an SD card. In 2024.1 Vitis you select CREATE BOOT IMAGE.The only think you need to do here is specify a path for the OUTPUTs and then select CREATE IMAGE.

11) This generates a BOOT.BIN. You can drop this file on an SD card. 

12) Power of the SOM/Carrier Card - Change the boot mode settings to SD Card Mode. 

13) Install the SD card in the SD card cage. 

14) Power on the SOM/Carrier Card.

15) You should see HELLO WORLD in the TERMINAL.

That's Hello World on almost any MPSoC platform.

The Vivado/Vitis instructions look good. The instructions helped me create the correct *.xsa file. I needed to refresh the board catalog/repository and select vendor avnet.com. Then the UltraZed-EV / EV Carrier Card board showed up and I clicked on the download button. I am using the
Vitis/Vivado 2023.2 versions.

I am still getting the same Vitis FSBLTimeout error. The platform and "Hello World" components build successfully. The Putty Terminal connects
correctly to the board. When I run the "Hello World" program the Putty window displays "Zynq MP First Stage" then the timeout error occurs. I set the IP Address and export VITIS_FSBL_EXIT_TIMEOUT=60000 in the Putty window. Is there something else I can check to fix the Vitis FSBL Timeout Error ?

I was just able to recreate this on a UltraZed-EV/EV Carrier Card without issue. It is 2024,1 but the same process should work for the other versions of the tools in a similar manner except maybe some differences in Classic Vitis for older tools where you can generate the examples from the application creation menu.

I used the FSBL provided in the project (ie - I didn't manually create an FSBL application).I followed the instructions I provided. I didn't need to do anything special to get to hello world.

I'm not sure why you are getting stuck with an FSBL Timeout Error.