The UltraZed-EG is still at 4A on VCCINT. What was your old designs utilization? Typically, at the time these boards are developed (engineering silicon phase) the XPE (Xilinx Power Estimator) could have been light.
Anyhow, do you remember what the overall design load was that caused you to bump up to the limit? It's hard to come up with a solution that fits everyone's needs (cost, size, ease of design-in).
The UltraZed-EV has a much larger VCCINT, but it is a larger and more expensive board.
On the next gen SOM (Versal AI Edge), that is coming, the VCCINT is being pushed to the Carrier Card so that an end-user can determine an exact solution for their needs.
Thanks for the reply.
Actually, I created a special design to test the power supply of the board. It had a lot of logic running at a high clock speed (80%, 400MHz). The design had enable bits to turn on data to individual sections so I could slowly increase power supply load. Unfortunately, on the Ultrazed-EG just loading the design into the FPGA fabric overloaded the VCCINT supply and rebooted the board. Just the clock tree current draw was sufficient to over current the POL.
Anything that does a lot of processing, like a digital receiver, could run into this problem. Many applications don't make heavy use of the FPGA and would work fine. It is just scary to know at any point you could hit a limit that does not let you use the full capability of the FPGA.
There will potentially be that person that utilizes the part and pushed the limits. You seem to be that person! The UltraZed-EG is a really dense board. There isn’t additional room to fit a larger solution as the rails are integrated into a multi-rail device.