I am using ZU3EG PS SPI0 with MIO, and SPI1 with EMIO in my project, and find SPI1 is not working. From the tests below,
1) Tested SPI0 with MIO using Xilinx example code, see CLK, MOSI, CS activities on board over scope; while SPI1 with EMIO using the same code, see no activities over ILA
2) Tested SPI0 with EMIO using the same code, see CLK, MOSI, CS activities over ILA; while SPI1 not change, and see no activities over ILA
3) Tested Xilinx ZCU102 Eval board (ZU9EG) with same FPGA and SDK code, both SPI0 and SPI1 have CLK, MOSI, CS activities over ILA
It looks like ZU3EG PS SPI1 has an issue, and it is OK with ZU9EG.
Frank
