Actions
Forum Thread Details
  • State Not Answered
  • Replies 18 replies
  • Subscribers 45 subscribers
  • Views 492 views
  • Users 0 members are here
Related

linux crash after PL load

Former Member

I have made a simple hardware design for the PL. I can load it with either JTAG or by cat'ing the file into xdevcfg. Once the hardware is loaded, it functions properly. Howver, all contact with the PS (running Linux) is gone. No terminal, no ethernet. Is it not possible to just load a bit file with no reference to the processor? Looking in the UCF there doesn't appear to be any reference to any processor specific IOs. I'm guessing that I need to route some PS dedicated pins to some specific hardware pins, but I would have thought that could be done without anything loaded into the PL at all. Any insight would be appreciated.

Parents
  • 0

    Bump

    I'm running a QNX port to the Zedboard (from a ZC702 version). I have a PL configuration file that uses the GP and ACP interfaces for interrupts and reading values from some BRAM using a CDMA.

    Everything runs great when I boot and the FSBL configures the logic. If I try and reconfigure the PL with the exact same PL configuration (bin file instead of a bit file), QNX still runs fine. But as soon as I try to access anything over the AXI, the whole system hangs as described above.

    Does anyone have any insight to this? Could it be a problem with the silicon revision shipped with the Zedboard...? I haven't seen anyone else describing this scenario on other forums except for a random errata case when you try and access OCM and DDR from the PL at the same time (which I'm not doing).

    Looking at the FSBL code compared to the Linux and QNX PL drivers, there seems to be a PL "initialization" that happens at boot. I'm wondering if something like that might be necessary when reconfiguring...

    I guess it could also be a problem with my PL design. Maybe a reset isn't going to every piece from the PS, so the PL is cranking away while the PS tries to reconfigure the PL. I wouldn't think this would result in a system crash, but this new kind of SoC has some strange quirks to it.

    Anyone else make any progress?

Reply
  • 0

    Bump

    I'm running a QNX port to the Zedboard (from a ZC702 version). I have a PL configuration file that uses the GP and ACP interfaces for interrupts and reading values from some BRAM using a CDMA.

    Everything runs great when I boot and the FSBL configures the logic. If I try and reconfigure the PL with the exact same PL configuration (bin file instead of a bit file), QNX still runs fine. But as soon as I try to access anything over the AXI, the whole system hangs as described above.

    Does anyone have any insight to this? Could it be a problem with the silicon revision shipped with the Zedboard...? I haven't seen anyone else describing this scenario on other forums except for a random errata case when you try and access OCM and DDR from the PL at the same time (which I'm not doing).

    Looking at the FSBL code compared to the Linux and QNX PL drivers, there seems to be a PL "initialization" that happens at boot. I'm wondering if something like that might be necessary when reconfiguring...

    I guess it could also be a problem with my PL design. Maybe a reset isn't going to every piece from the PS, so the PL is cranking away while the PS tries to reconfigure the PL. I wouldn't think this would result in a system crash, but this new kind of SoC has some strange quirks to it.

    Anyone else make any progress?

Children