I seem to be having a weird issue where I have a ISE project navigator project that works fine, but the second I ported the design to the Planahead and the EDK I am receiving errors.
The core in question is just a VGA core and the constraints were taken from the zedboard master constraints file.
The main problem stems from the following critical warnings that are generated, these prevent me from actually generating the bitfile:
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_0' at site Y21, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_0 on site Y21 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:12]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_1' at site Y20, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_1 on site Y20 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:13]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_2' at site AB20, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_2 on site AB20 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:14]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_3' at site AB19, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_3 on site AB19 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:15]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_0' at site AB22, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_0 on site AB22 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:16]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_1' at site AA22, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_1 on site AA22 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:17]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_2' at site AB21, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_2 on site AB21 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:18]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_3' at site AA21, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_3 on site AA21 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:19]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_0' at site V20, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_0 on site V20 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:20]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_1' at site U20, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_1 on site U20 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:21]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_2' at site V19, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_2 on site V19 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:22]
[Constraints 18-5] Cannot loc instance 'arm_ps_i/vga_0/vga_0/vga_red_3' at site V18, Illegal to place instance arm_ps_i/vga_0/vga_0/vga_red_3 on site V18 [C:/Users/cwilson/Documents/Projects/OV7670_PA14-2/OV7670_PA14-2.srcs/sources_1/edk/arm_ps/data/arm_ps.ncf:23]
This is frustrating because the link at the side to the lines in the ncf go directly to the constraints file which have:
NET vga_0_vga_blue_pin[0] LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1"
NET vga_0_vga_blue_pin[1] LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2"
NET vga_0_vga_blue_pin[2] LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3"
NET vga_0_vga_blue_pin[3] LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4"
NET vga_0_vga_green_pin[0] LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1"
NET vga_0_vga_green_pin[1] LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2"
NET vga_0_vga_green_pin[2] LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3"
NET vga_0_vga_green_pin[3] LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4"
NET vga_0_vga_red_pin[0] LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1"
NET vga_0_vga_red_pin[1] LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2"
NET vga_0_vga_red_pin[2] LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3"
NET vga_0_vga_red_pin[3] LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4"
NET vga_0_vga_hsync_pin LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS"
NET vga_0_vga_vsync_pin LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS"
Those are the correct pin names taken from the ports tab in the Edk
I know that these nets CAN be placed there and again, this was copied from the Zedboard master constraints. Additionally, it seems odd that although the warning link to these lines it keeps only referring to vga_red_X and not any of the other colors. Has anyone else seen an issue with the VGA pins in the planahead project? Has anyone successfully mapped to these pins in planahead through an EDK project?
Thanks!
