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Integrate System Generator and ARM

Former Member

Hi All,

Here is a description of what I am trying to do. Please provide any pointers/ref designs or suggestions that will help me complete the design.

1. I have a complex design in System Generator for a Wireless Radio pipeline. This design requires a binary stream of data typically tens of Megabit to configure the design and also contain the data that need to be transmitted over the air using the radio pipeline.

2. This binary configuration data is generated by a C program which I intend to run on the Arm core.
Basically, I want the C program to write a bunch of bits in a FIFO that resides in the PL and the system generator design will pick it up from there and do its thing (this part is done).

In the past I have compiled the sysgen design to the target fpga and then use the .ngc file to instantiate in the top-level HDL and use ISE toolchain to generate the bit file.

For this case I think I will have to use XPS to include the radio design as a peripheral or custom IP and then use the AXI interface to talk to that. Does anybody has any idea how can I accomplish this, that is the interfacing of the sysgen design to the processor subsystem. Any ref designs would be very helpful.

Any pointers are greatly appreciated.

Thanks
-Aveek

  • 0

    adutta,

    This may help:

    http://zynqgeek.blogspot.com/2012/09/creating-custom-peripheral.html

    If you open up the user_logic.vhd file (or what it is called if you choose to have the stub created in verilog), you will see a great deal of comments in the file explaining where to place 'custom code'.

    You can either instantiate your ngc file here, or you can bring out the signals you need to the top of your user_logic, and then your custom peripheral file, and connect them as external ports within EDK.

    I will see if I can put together a short how-to on this today.

  • 0 in reply to Former Member

    The example was helpful but it is a very simple one. In my case, I am hoping to send few tens of megabit to my custom peripheral and I believe that I will have to use the AXI master interface to send that across to the PL, instead of the AXI-Lite, for faster data transfer. I just need the data and a data_valid signal at the other end. Those are the two top-level input ports in my sysgen design along with a clock and clk_enable which I do not know yet where to source from. I will wait for you to create the example you had mentioned but any how-to's on AXI bus implementation will very helpful.

    Thank you again for all the awesome tutorials for Zynq. Those are very helpful to get started on this platform.

  • 0

    Zynqgeek - I was able to use the "EDK export" function in Sysgen to export my design as a "pcore" along with the necessary AXI4 interface. There are examples in the Sysgen user guide on how to do this. The export also creates the drivers required to poke at the shared memories/registers that interface to the sysgen design. Once the pcore is generated I can add it to my processor design as a user IP along with the relevant connections to the AXI interface IP. Then connect the clock ports to my design and that's it. Generate bit file and export to SDK. The Sysgen example also provides an example application that uses the drivers and interacts with the design.

    All I need to do now is to be able to program the FPGA using Linux and compile the application program in the Linux core. I guess then it won't be a bare metal design. If you know of any resources regarding this then please let me know.

    Thank you in advance. All the tutorials have been awesome.