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ZedBoard Hardware Design Add Hardware to Programmable Logic
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Related

Add Hardware to Programmable Logic

Former Member
Former Member over 12 years ago

Hello,

i created a base system for Zedboard with BSB.
Now i want to add Hardware (a simple counter) described in VHDL to the Programmable Logic part of the zynq chip.
I don't want to connect it to the AXI Bus or anything, just want to connect it to switches and leds of the board.

I added the .vhd file to the project and i'm able to simulate the counter.

But i can't assign the ports from the entity to pins of the zynq chip.
ENTITY counter IS
    PORT (
tclk tt: IN  tSTD_LOGIC;
        res             : IN    STD_LOGIC;
tstarttt: IN  tSTD_LOGIC;
tqtt: OUT  tSTD_LOGIC
        );
END counter;

What do i have to do to make the ports avaiable in PlanAhead and to use a contraints file to assign them to pins?

Thank you in advance!

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  • bhfletcher
    0 bhfletcher over 12 years ago

    You will need a top-level wrapper that includes your PS7 system as well as an instantiation for your counter. Your top-level will need a port list that includes your counter pins. Then you can add a constraints file that constrains the PL pins.

    Bryan

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  • Former Member
    0 Former Member over 12 years ago

    I have the similar problem. I have added the AXI UART Lite and I want to connect it to PL pins. I created the UCF file with the following lines:


    NET axi_uartlite_0_RX_pin IOSTANDARD=LVCMOS25 | LOC=F18;
    NET axi_uartlite_0_TX_pin IOSTANDARD=LVCMOS25 | LOC=E18;

    But it gives me the bitten error.


    Thanks

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  • metinburak_
    0 metinburak_ over 12 years ago in reply to Former Member

    Can you send the error code?
    It can be because the top level wrapper file might not have been updated when you exit the XPS.
    All the pins in UCF must exist in the top level wrapper vhdl or verilog file's interface.

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  • Former Member
    0 Former Member over 12 years ago in reply to Former Member

    All of the pins for a given IO Bank, Bank 35 connected to the FMC connector in this case, must be set to the same IO standard. Since you have selected LVCMOS25 for these signals make sure that the remaining IO in Bank 35 either have no IO standard defined or that they are also set to LVCMOS25.

     

    Also make sure that J18 is set for 2.5 V and not the 1.8V default. Since the FMC interface spans both Bank 35 and 34 you need to make sure any signals on Bank 34 are set to LVCMOS25 if they are being used.

     

    You can see the IO bank groupings in the master Zedboard ucf file: http://www.zedboard.org/documentation/1521

     

    -Gary

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