Hi there,
i've been successful at creating different kind of IPs, mostly in AXi lite etc..
I would like to implement DMA in the zynq and i could need some help:
DMA streams of data from FPGA to CPU
I have gathered many tutorials & stuff but i still am not able to implement a streaming IP to create a DMA transfer, could some one explain me how to proceed at connecting everything?
If i got it right:
we need to use the streaming protocol (might be even easier than AXi lite, fewer signals);
We need to use a DMA IP from the IP catalog and it seems the DMA engine would be the one, but i still hesitate with CDMA. The only difference which makes me tend to use DMA engine is that it has a Bus Interface allowing connexion to what should be a custom IP while the other doesn't have any. May be wrong?
So we add the DMA IP from catalog.
Then we have two options:
ACP: accelerator coherent port to transfer data to the MEMORY CACHE
HP high perf port to transfer data to DDR RAM (better?)
tend to use the HP options
then i need two HP one for write one for read. We can modify the accessible addresses which, as i understand it, will be the addresses inside the DDR RAM.