Hi Folks,
I'm trying to build custom IP which collects data from peripherals. Then I want this module integrated with AXI stream interface, which can connect a DMA to transfer the data to DDR memory, since the AXI DMA ip only has axi interface to hook up with other modules.
I followed the some instructions to generate a blank IP with AXI-stream interface in verilog using the Create, Import Peripheral Wizard (CIP) inVivado 2013.4. But I didn't find any reference design or document to show how to revise the IP.
What I want to is like:
To add custom ports to IP
To add a timer insider the IP.
To send data from the IP to DMA periodly.
Any other suggestion?
thx a lot.
Sam