Free FFT Co-Processor with AXI Interfaces

Hi,

last week I have uploaded a new version of my FFT co-processor bel_fft. This version comes now with AXI interfaces (slave for configuration and master for memory access).
It is configured via a graphical Java wizard, that also creates
testbenches and simulation scripts for ISim, XSim, and ModelSim, as well as all necessary side files to integrate the core into XPS.
This might also be interesting for those who are currently developing their own AXI components. The core is written in Verilog and was tested on the ZC702 board.
It is distributed under the GNU LGPL 2.1 and can be found under
http://sourceforge.net/projects/belfft
Please keep in mind that the core is still under development so any feedback is welcome!

0 Former Member over 13 years ago

Hi fstorm,
this seems to be a really usefull module.
I'm also analyzing your code on how you are using AXI master for access DDR via AXI High Performance Port.

Thanks,
Gabriele
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0 Former Member over 13 years ago

fstorm,

Thanks for making this available for the Zynq. I've managed to make the FFT design work on the ZedBoard with WebPACK 14.4. However, there is an issue with the coregen tool, for which you must apply a workaround for bel_fft to work: http://www.xilinx.com/support/answers/53695.htm

I've applied the second of the listed workarounds (setting the env variable XIL_CG_LOAD_ALL_FAMILIES=true) before running bel_fft and the PlanAhead session used for building the design.

You may wish to add this to the documentation to save your users' time.

Thanks again.
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0 Former Member over 13 years ago

Hi Tom,

thanks for the hint! Yes, I think it is a good idea adding this to the documentation.
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