Hi ZedBoard Community,
i am using a ZedBoard to communicate with an adc via axi_spi interface.
The axi_spi core is powered by FCLK1 with 100 MHz, devided by 8, so the frequency of the spi clock should be at 12.5 MHz.
So far the theory.
I measured the clock frequency to be at around 18 MHz, which is much too fast for the GPIO Pins of the ZedBoard (the logic levels are not reached in time).
Do you know the reason for that? Is there an error in the clock regulator modul of the zynq or somewhere else?
Did i make a mistake with the calculations?
Thank you in advance for every hint/comment.
Best Regs,
Charles
