I encountered a problem when i generate the bitstreem of Reference design for Zedboard and AD-FMCOMMS2-EBZ with PlanAhead14.4.The problem is:ERROR:EDK:2951 -
Unknown Tcl procedure ::hw_axi_ad9361_v1_00_a::run_coregen called
ERROR:EDK - axi_ad9361_0 (axi_ad9361) -
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_processing_system7_0_wrapper.ngc] u00B4u00EDu00CEu00F3 2
ERROR:EDK -
Error while running "make -f system.make netlist".
ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [D:/Zedboard/sdr14_4/cf_ad9361_zed/__xps/pa/_system_synth.tcl]
.
My design tool version is ise14.4,and i download the HDL design from http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl.
Any help you can provide will be much appreciated.
Thanks!
