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ZedBoard Hardware Design FMC Clk Question
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FMC Clk Question

Former Member
Former Member over 13 years ago

Hi Zedboard form! I have a quick question:

I am trying to attach a camera through the FMC LPC port on the zedboard.

In my own project, and in the design project in the avnet document "FMC-IMAGEON Building a Video Design from Scratch Tutorial," I get the same error generating the bitfile. It reads:

"
[Bitgen 342] This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.  This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.  To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation.  To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow
This message applies to the following I/O ports:
   fmc_imageon_hdmi_in_0_clk_pin
"

In addition, I also get the critical warning related to that same pin:

"
[Constraints 18-5] Cannot loc instance 'fmc_imageon_hdmi_in_0_clk_pin_BUFGP/BUFG' at site D18, Illegal to place instance fmc_imageon_hdmi_in_0_clk_pin_BUFGP/BUFG on site D18 ["C:/Users/cwilson/Documents/Projects/Zedboard-FMC-IMAGEON/Zed-FMC_IMAGEON/Zed-FMC_IMAGEON.srcs/sources_1/edk/proc_module/data/proc_module.ncf":34]
"

In the UCF for the Project:

NET "fmc_imageon_hdmi_in_0_clk_pin"                LOC = "D18"; # HDMII_LLC   - FMC1-G2  (CLK1_M2C_p)

NET fmc_imageon_hdmi_in_0_clk_pin TNM_NET = hdmii_clk;
TIMESPEC TS_hdmii_clk = PERIOD hdmii_clk 148500 kHz;

I really have no clue what to do here...Has anyone come across this issue? Did you just demote the error to a warning?

Thanks!

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  • Former Member
    0 Former Member over 13 years ago

    After referencing the Zedboard schematics,

    ref link: http://zedboard.org/sites/default/files/documentations/ZedBoard_RevC.1_Schematic_120913_0.pdf

    On sheet 9 you see that D18 is the FMC-CLK1_P (the possitive side of the differential clock pair 1 that goes to the FMC card).  If we follow that over to sheet 2, we see that FMC-CLK1_P goes to Pin G2 on the FMC card.

    Now, referencing the FMC-IMAGEON schematic,

    reflink: https://www.em.avnet.com/Support%20And%20Downloads/AES-FMC-IMAGEOV-G_SCH_V0H.PDF (note: requires avnet login, which is free).

    we can see on page 2 G2 on the FMC connector goes to page 4 and the camera connector.

    Now we have validated that it looks to go the right place (which there really isn't any reason to think it wouldn't, but never a bad exercise to do), we need to look at the pin on the Zynq device that is being used.  The pin's name is "IO_L12P_T1_MRCC".

    refencing this document:
    http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

    MRCC is the part of this pin that we are interested in.  MRCC stands for Multi Region Clock Capable.  In the 7-Series devices (which includes Zynq) we have a number of clocking pins to pick from.  In this case, a MRCC was picked, and is valid to drive a clock out of.

    With all of that said (and it was a lot), I see no reason why you should be getting that error.  From our findings here there is no reason why that -g option would harm the FPGA fabric or IO structures.  I think you are safe to move ahead with that.  I'll ping the author of the "FMC-IMAGEON Building a Video Design from Scratch Tutorial" and see what his thoughts are.

    Let me know how yo make out.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Thanks! It does seem that you just have to demote the bitgen error to a warning and it will work fine.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    wilsonchrec,

    We're you successful in just demoting it?  If so, I'll open a case with Xilinx to see what their thoughts are on why the warning is even thrown.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Its seems like you can just demote the "Bitgen Error" and then from that point forward it is a "Critical Warning" and will appear every time.

    I chipscoped the signal in my design and it seems to work just fine.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Its seems like you can just demote the "Bitgen Error" and then from that point forward it is a "Critical Warning" and will appear every time.

    I chipscoped the signal in my design and it seems to work just fine.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    wilsonchrec,

    Thanks so much for the update.  I'll pass it along to the factory.

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