The ZedBoard Hardware Users Guide, as well as the ZedBoard Rev C.1 Errata and the ZedBoard Rev D.2 Errata documents, have been updated to reflect that the ZedBoard DDR3 Single-Ended PCB Trace Impedance does not match the recommendations in the Xilinx document Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933). The updated documents can be found here: http://zedboard.org/documentation/1521
There are no known field failures due to this issue. The ZedBoard ships with a -1 speed-grade Zynq device which is capable of a DDR3 interface speed of 533 MHz. The ZedBoard DDR3 has been tested at frequencies higher than this and passed. However, for those designers looking to duplicate the ZedBoard design, you should carefully consider what Xilinx specifies in UG933 as well as your own design objectives to determine how best to route you own board.
-Gary