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ZedBoard Hardware Design 1V Power supply under-powered
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1V Power supply under-powered

Former Member
Former Member over 13 years ago

What's the maximum power that can by drawn by the Zynq PL? Has this been tested?

I have build a large design (80%) that need to runs at 100MHz, but when I program the bitstream to the Zedboard. The Zynq reset a few ms after being DONE.

Also, I have probed the 1V power supply at C357. After, the PL is DONE, the voltage go down to about 560mV and go back up to 1V probably because the PL resets.

What could be causing this?

Is it because the PL draw to much power?

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  • Former Member
    0 Former Member over 13 years ago

    I have done some further analysis on this matter. I have found in the Zedboard user guide that the budgeted ammount of power for the PL is 1.2A on 1V PSU.

    However, using Xilinx Power Analyser, I see that my design can drawn as much as 1.3A. See http://www.louif.com/power_analysis.png .

    Also, to verify that it was the power drawn that made the Zynq reset and not some other design flaw, I added clock gating so that much of the design would not draw power at startup. And indeed, in that case, Linux boots just fine. But still, as soon as I activate the clock in the design, the Zynq resets.

    I measure the voltage on the 1V rail using an oscilloscope during reset. You may see the results here: http://www.louif.com/ADS00001.BMP

    Is there any plan to beef up the 1V PSU so that it can handle a full load? This seems to be like a show-stopper.

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  • Former Member
    0 Former Member over 13 years ago

    I have done some further analysis on this matter. I have found in the Zedboard user guide that the budgeted ammount of power for the PL is 1.2A on 1V PSU.

    However, using Xilinx Power Analyser, I see that my design can drawn as much as 1.3A. See http://www.louif.com/power_analysis.png .

    Also, to verify that it was the power drawn that made the Zynq reset and not some other design flaw, I added clock gating so that much of the design would not draw power at startup. And indeed, in that case, Linux boots just fine. But still, as soon as I activate the clock in the design, the Zynq resets.

    I measure the voltage on the 1V rail using an oscilloscope during reset. You may see the results here: http://www.louif.com/ADS00001.BMP

    Is there any plan to beef up the 1V PSU so that it can handle a full load? This seems to be like a show-stopper.

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