I've added xililnx Ext AXI Slave connector (DS805) (AXI4). I am trying to accomplish an AXI write from the PS. So from what I have read, my "slave" is considered my PL section. I am using logic to set the slave signals. Below is a system port assigment. So any of the ports that are considered "in" I can set in the PL. The ports that are "out" are coming from my PS. I am letting the PS act as my "master". My question is how do I set things such as AWID, AWLEN, AWBURST, etc. I am running embedded linux on my zedboard. I have been searching for an example driver to set "master" signals. can anyone help me with this?
My ultimate goal is to be able to write data from my embedded linux server to data registers in the PL as well as the ability to read data from the PL back into my embedded linux server. I need more than 32 registers otherwise I would use AXI4-lite. At this time I am just using 256 registers (32bits).
Any help would be greatly appreciated!
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0); processing_system7_0_PS_SRSTB_pin : in std_logic; processing_system7_0_PS_CLK_pin : in std_logic; processing_system7_0_PS_PORB_pin : in std_logic; processing_system7_0_DDR_Clk : inout std_logic; processing_system7_0_DDR_Clk_n : inout std_logic; processing_system7_0_DDR_CKE : inout std_logic; processing_system7_0_DDR_CS_n : inout std_logic; processing_system7_0_DDR_RAS_n : inout std_logic; processing_system7_0_DDR_CAS_n : inout std_logic; processing_system7_0_DDR_WEB_pin : out std_logic; processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); processing_system7_0_DDR_ODT : inout std_logic; processing_system7_0_DDR_DRSTB : inout std_logic; processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0); processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_VRN : inout std_logic; processing_system7_0_DDR_VRP : inout std_logic; processing_system7_0_FCLK_CLK0_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_BID_pin : in std_logic_vector(11 downto 0); axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RID_pin : in std_logic_vector(11 downto 0); axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_RLAST_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_AWID_pin : out std_logic_vector(11 downto 0); axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_AWLEN_pin : out std_logic_vector(7 downto 0); axi_ext_slave_conn_0_M_AXI_AWSIZE_pin : out std_logic_vector(2 downto 0); axi_ext_slave_conn_0_M_AXI_AWBURST_pin : out std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0); axi_ext_slave_conn_0_M_AXI_WLAST_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_ARID_pin : out std_logic_vector(11 downto 0); axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_ARLEN_pin : out std_logic_vector(7 downto 0); axi_ext_slave_conn_0_M_AXI_ARSIZE_pin : out std_logic_vector(2 downto 0); axi_ext_slave_conn_0_M_AXI_ARBURST_pin : out std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic );
