Hi all,
Beginning, I created a custom peripheral (with CIP XPS) and I used the 32 GP AXI Master to connect the PS with my accelerator in PL (AXI-Lite). The data is sent from PS to PL, then traitemnt is done via the hardware accelerator, finally the data returned from PL to PS :
unsigned int Tab [4];
*r0= Tab[0];
*r1= Tab[1];
*r2= Tab[2];
*r3= Tab[3];
Tab[0] = *r0;
Tab[1] = *r1;
Tab[2]= *r2;
Tab[3] = *r3;
And I got a correct result.
Now, since the data is stored in the DDR, I want that my accelerator uses the high performance (HP) 64 bit slave port to directly access to DDR. So, I created a custom peripheral (with CIP XPS), I choose AXI4 burst capable high-throughput memory mapped interface. After that, I connected the slave of my IP to AXI-Lite Master of PS and the master (64 bit) of IP to the HP slave port of PS.
The problem that I can't found any solution or tutoral wich explain how I send the adress of the Tab which allow to the IP to access to ddr. How the PL can access directly to the data of Tab??
Any help please??
Moktar.
