Creating an AXI peripheral with reconfigurable modules

Hi everybody,

I'm developing an architecture based on the ARM PS + some custom peripheral in the programmable logic. I'm using Vivado HLS to create the peripherals and packaging them with AXI interfaces in order to use the provided driver in the SDK.

Since I want to implement partial reconfiguration capabilities I'm also using the PCAP, following a tutorial, to change the datapath inside these AXI4 peripheral. I have a really basic configuration which works well.

My question is: how can I use Vivado HLS to create from sratch a new AXI4 peripheral which has an AXI4 enclosure and a reconfigurable black box inside (where I can put different datapaths)?

Thanks in advance,

Emilio

0 Former Member over 9 years ago

Hello Emilio,

You question is pretty specific to using the Xilinx HLS tools as opposed to a question about the ZedBoard or one of the other Avnet SOMs such as the MicroZed, PicoZed, Mini-ITX, etc. If one of our forum members has some experience with this please do respond.

Otherwise posting the question to one of the Xilinx Community forums generally, https://forums.xilinx.com/ or the Xilinx High Level Synthesis Forum specifically. https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
might be more productive.

Please share anything you do find out.

-Gary
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0 Former Member over 9 years ago in reply to Former Member

Thanks for the link. I'll try on the Xilinx forum.
For now I understood that to create a design with IPs with Reconfigurable Modules inside themself it is better to work directly with HDL files.
Maybe if using Vivado HLS is a priority is better to reconfigure the entire IP and not a Reconfigurable Partition inside it.
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